Embedded systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent, and connected computing systems. By bringing together three leading conferences [the Int...
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Real-time constraint is one of the most common challenges found in many critical embedded applications, namely image and video processing. However, software tools such as Matlab and general purpose microprocessor are ...
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In this paper, we propose a new hardware Trojan Design. This design makes all HT trigger inputs have the same impact as functional inputs on output signals. It is difficult to distinguish between trigger inputs and fu...
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ISBN:
(纸本)9781728191980
In this paper, we propose a new hardware Trojan Design. This design makes all HT trigger inputs have the same impact as functional inputs on output signals. It is difficult to distinguish between trigger inputs and functional inputs. Simultaneously, trigger inputs will not be identified as redundant inputs. This approach can defeat the existing detection methods which identify weakly affecting and red Cant trigger inputs across multiple sequential levels. The proposed HT has stealthiness and general applicability.
Runtime Integrated Custom Execution (RICE) relocates traditional peripheral reconfigurable acceleration devices into the pipeline of the processor. This relocation unlocks fine-grained acceleration previously impeded ...
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ISBN:
(纸本)9781450369251
Runtime Integrated Custom Execution (RICE) relocates traditional peripheral reconfigurable acceleration devices into the pipeline of the processor. This relocation unlocks fine-grained acceleration previously impeded by communication overhead to a peripheral accelerator. Preliminary simulation results on a subset of the PARSEC benchmark suite shows promise for RICE in HPC applications.
In the domain of model-based design, the main challenge is to provide a model with a set of conditions and algorithms to ensure that the designed system produces correct results. A dataflow based model called Actors w...
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ISBN:
(纸本)9781728191980
In the domain of model-based design, the main challenge is to provide a model with a set of conditions and algorithms to ensure that the designed system produces correct results. A dataflow based model called Actors with Stretchable Access Patterns (ASAP) has been recently proposed, which takes the behavior of functional blocks on real architectures, especially FPGAs, into account. In this work, we present the framework of techniques to analyze the correctness of designs based on the ASAP model and to determine a set of modifications that must be applied to faulty cases to ensure the conformance of all actors. The principles are illustrated by a realistic application.
With increasing applications of Deep Neural Networks (DNNs) to edge computing systems, security issues have received more attentions. Particularly, model stealing attack is one of the biggest challenge to the privacy ...
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ISBN:
(纸本)9781728191980
With increasing applications of Deep Neural Networks (DNNs) to edge computing systems, security issues have received more attentions. Particularly, model stealing attack is one of the biggest challenge to the privacy of models. To defend against model stealing attack, we propose a novel protection architecture with fuzzy models. Each fuzzy model is designed to generale wrong predictions corresponding to a particular category. In addition, we design a special voting strategy to eliminate the systemic errors, which can destroy the dark knowledge in predictions at the same time. Preliminary experiments show that our method substantially decreases the clone model's accuracy (up to 20%) without loss of inference accuracy for benign users.
This paper presents a secure hardware architecture of an image sensor to accelerate feature extraction using region-level parallelism. For each logical region, the design includes a region processing unit (RPU) with a...
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ISBN:
(纸本)9781728191980
This paper presents a secure hardware architecture of an image sensor to accelerate feature extraction using region-level parallelism. For each logical region, the design includes a region processing unit (RPU) with an attention module (AM). The AM activates the processing in the RPU if there are no spatiotemporal redundancies. It reduces power consumption and data volume by utilizing the concepts of predictive coding. Also, every RPU has a crypto-core driven by the AM to withstand against adversaries. Simulation results show we can save 89.70% power with a significant speedup.
In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of th...
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ISBN:
(纸本)9781450369237
In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of the optimal energy cache configuration for application phases for the instruction and data caches.
High-level synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/systemC) into a register-transfer level (RTL) implementation. However,...
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ISBN:
(纸本)9781728191980
High-level synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/systemC) into a register-transfer level (RTL) implementation. However, an error may exist in the RTL implementation from the compiler in the high-level synthesis due to the complex and error prone compiling process. Global common subexpression elimination (GCSE) is a commonly used code motion technique in the scheduling of high-level synthesis. In this paper, we present an equivalence checking method to verify GCSE in the scheduling of high-level synthesis by enhancing the path equivalence criteria. The initial experimental results demonstrate our method can indeed verify the GCSE which has not been properly addressed in the past.
It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promisi...
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ISBN:
(纸本)9781728191980
It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promising result, which however suffers from a high computation cost. In this paper, we design a new heatmap-aware method to defend adversarial attacks, leading to a significant decrease in the time cost. To he specific, we compute the classification importance from each part of the input to obtain the heatmap of the data, and the key areas of classification are extracted according to the heatmap. A series of transformations are applied to the key areas of the classification, which reduces the amount of data to be processed and thus reduces the time cost. A set of preliminary experiments are conducted to testify the effectiveness of the proposed approach.
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