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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 853 条记录，以下是121-130 订阅

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Future wireless convergence platforms

Future wireless convergence platforms

引用

international conference on hardware/software codesign and system synthesis

作者： Glossner, J Moudgill, M Iancu, D Nacer, G Jintukar, S Stanley, S Samori, M Raja, T Schulte, M Vassiliadis, S Sandbridge Technol Inc White Plains NY 10601 USA

ISBN: (纸本)1595931619

As wireless platforms converge to multimedia systems, architectures must converge to support voice, data, and video applications. From a processor architecture perspective, support for signal processing (both audio and video), control code, and Java execution will be required in a convergent device. Traditionally, wireless communications systems have been implemented in hardware. Convergent devices must be able to roam seamlessly across multiple communications systems. To avoid excessive hardware costs, a software Defined Radio (SDR) approach offers a programmable and dynamically reconfigurable method of reusing hardware to implement physical layer processing. In this paper, we discuss trends in wireless platforms which are inherently convergence platforms. We also present the Sandbridge state-of-the-art example platform that supports both communications and multimedia applications processing. The architecture efficiently executes Java, Digital Signal Processing (DSP), and control code. Architectural features that reduce power dissipation and enable real-time processing are described. All of the communications and multimedia processing is executed completely in software without specialized hardware support. The processor is programmed in C with supercomputer-class compiler support for automatic vectorization, multithreading, and DSP semantic analysis.

关键词： software defined radio wireless digital signal processors

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software/hardware codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level synthesis and Register-Transfer Level Design Methodologies 29

Software/Hardware Codesign of the Post Quantum Cryptography ...

引用

29th international conference on Field-Programmable Logic and Applications (FPL)

作者： Farahmand, Farnoud Duc Tri Nguyen Dang, Viet B. Ferozpuri, Ahmed Gaj, Kris George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA

ISBN: (纸本)9781728148847

When quantum computers become scalable and reliable, they are likely to break all public-key cryptography standards, such as RSA and Elliptic Curve Cryptography. The projected threat of quantum computers has led the U.S. National Institute of Standards and Technology (NIST) to an effort aimed at replacing existing public-key cryptography standards with new quantum-resistant alternatives. In December 2017, 69 candidates were accepted by NIST to Round 1 of the NIST Post-Quantum Cryptography (PQC) standardization process. NTRUEncrypt is one of the most well-known PQC algorithms that has withstood cryptanalysis. The speed of NTRUEncrypt in software, especially on embedded software platforms, is limited by the long execution time of its primary operation, polynomial multiplication. In this paper, we investigate speeding up NTRUEncrypt using software/hardware codesign on a Xilinx Zynq UltraScale+ multiprocessor system-on-chip (MPSoC). Polynomial multiplication is implemented in the Programmable Logic (PL) of Zynq using two approaches: traditional Register-Transfer Level (RTL) and High-Level synthesis (HLS). The remaining operations of NTRUEncrypt are executed in software on the Processing system (PS) of Zynq, using the bare-metal mode. The speed-up of our software/hardware codesigns vs. purely software implementations is determined experimentally and analyzed in the paper. The results are reported for the RTL-based and HLS-based hardware accelerators, and compared to the best available software implementation, included in the NIST submission package. The speed-ups for encryption were 2.4 and 3.9, depending on the selected parameter set. For decryption, the corresponding speed-ups were 4.0 and 6.8. In addition, for the polynomial multiplication operation itself, the speed up was in excess of 75. Our code for the NTRUEncrypt polynomial multiplier accelerator is being made open-source for further evaluation on multiple software/hardware platforms.

关键词： Post-Quantum Cryptography lattice-based NTRU hardware/software codesign High-Level synthesis

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hardware estimation and synthesis for a codesign system

Hardware estimation and synthesis for a codesign system

引用

international conference on Signal Processing, Communications and Networks

作者： Sangeetha, M. Perinbam, J. RajaPaul Revathy Anna Univ Coll Engn Dept Elect & Commun Engn Madras 600025 Tamil Nadu India SA Engn Coll Dept Elect & Commun Engn Madras Tamil Nadu India

ISBN: (纸本)9781424409969

A software model of hardware estimator is developed. The behavioral description is transformed into an intermediate format called Control Flow Graph (CFG). The graph is partitioned into hardware and software. The unoptimized hardware in intermediate graph is estimated by transforming the graph into matrix format. The partitioned hardware of Control Flow Graph is translated as behavioral network graph. The High Level synthesis and Logic synthesis are performed using the BNG with simple logical transformation. The final RTL obtained from the conventional synthesis method and BNG method for resource and timing constraint were presented. The cost estimation for the various control construction is being tabulated.

关键词： Codes (symbols)

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A Case of system-level hardware/software Co-design and Co-verification of a Commodity Multi-Processor system with Custom hardware 12

A Case of System-level Hardware/Software Co-design and Co-ve...

引用

10th ACM international conference on hardware/software-codesign and system synthesis

作者： Hong, Sungpack Oguntebi, Tayo Casper, Jared Bronson, Nathan Kozyrakis, Christos Olukotun, Kunle Oracle Labs Belmont USA Stanford University Palo Alto USA

ISBN: (纸本)9781450314268

This paper presents an interesting system-level co-design and co-verification case study for a non-trivial design where multiple high-performing x86 processors and custom hardware were connected through a coherent interconnection fabric. In functional verification of such a system, we used a processor bus functional model (BFM) to combine native software execution with a cycle-accurate interconnect simulator and an HDL simulator. However, we found that significant extensions need to be made to the conventional BFM methodology in order to capture various data-race cases in simulation, which eventually happen in modern multi-processor systems. Especially essential were faithful imp lementations of the memory consistency model and cache coherence protocol, as well as timing randomization. We demonstrate how such a co-simulation environment can be constructed from existing tools and software. Lessons from our study can similarly be applied to design and verification of other tightly-coupled systems.

关键词： Co-Verification Co-Simulation Bus Functional Model FPGA Prototyping Transactional Memory

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A PCM Translation Layer for Integrated Memory and Storage Management 14

A PCM Translation Layer for Integrated Memory and Storage Ma...

引用

international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Chang, Bing-Jing Chang, Yuan-Hao Chang, Hung-Sheng Kuo, Tei-Wei Li, Hsiang-Pang Macronix Int Co Ltd Emerging Syst Lab Hsinchu Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan Acad Sinica Inst Informat Sci Taipei Taiwan Acad Sinica Res Ctr Informat Technol Innovat Taipei Taiwan

ISBN: (纸本)9781450330510

Phase change memory (PCM) is known for its potentials as main memory and as storage. In contrast to the past work, this work presents a PCM translation layer that considers how the main memory is used by the operating system together with the usage patterns of storage by trading their performance and reliability. In particular, a joint management scheme is proposed to improve the capability of PCM as both main memory and storage so as to enhance the performance of the entire system. The endurance issue of PCM for main memory is resolved by utilizing the potentially large capacity of the PCM storage space with limited modifications to the existing operating system implementations. Moreover, three commands are proposed to help operating system engineers to take advantage of PCM as main memory and storage by reducing I/O overheads and speeding up both the initialization and termination of program executions. The experimental results show that the performance of PCM as both main memory and storage can be significantly improved with reasonable lifetime, while the system overhead is very limited under coarse-grained wear leveling.

关键词： operating systems (computers) phase change memories program verification storage management I/O overheads PCM storage space PCM translation layer coarse-grained wear leveling integrated memory management integrated storage management joint management scheme operating system operating system implementations phase change memory program executions hardware Joints Memory management Operating systems Performance evaluation Phase change materials Random access memory Store management Operating systems Phase change memory main memory Pulse code modulation PROGRAM EXECUTION random access machine program verification Phase change materials Computer hardware Joints Joints Performance Evaluation

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synthesis of Real-Time Embedded software with Local and Global Deadlines 03

Synthesis of Real-Time Embedded Software with Local and Glob...

引用

First IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003

作者： Hsiung, Pao-Ann Lin, Cheng-Yi Department of Computer Science National Chung Cheng University Chiayi-621 Taiwan

ISBN: (纸本)1581137427

Current methods cannot synthesize real-time embedded software applications when the global deadline of a task is shorter than the total of all local deadlines along a critical path in the task. This creates unnecessary modeling limitations which directly affect the types of systems synthesizable. We propose a quasi-dynamic scheduling algorithm for simultaneously guaranteeing both local and global deadlines, while satisfying all precedence constraints among sub-tasks and among tasks. Through this scheduling procedure, we are able to formally synthesize real-time embedded software from a network of Real-Time Petri Nets specification. Application examples, including a driver for the Master/Slave role switch in Bluetooth wireless communication devices, are given to illustrate the feasibility of the scheduling algorithm.

关键词： Embedded systems

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hardware neural network accelerators

Hardware neural network accelerators

引用

11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Temam, O. INRIA Saclay France

""Because of increasingly stringent energy constraints (e.g., Dark Silicon, there is a growing consensus in the community that we may be moving towards heterogeneous multi-core architectures, composed of a m... 详细信息

ISBN: (纸本)9781479914173

关键词： application specific integrated circuits fault tolerant computing graphics processing units learning (artificial intelligence) multiprocessing systems neural nets parallel architectures power aware computing

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Highly-cited ideas in system codesign and synthesis 08

Highly-cited ideas in system codesign and synthesis

引用

Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Vahid, Frank Givargis, Tony Department of Computer Science and Engineering University of California Riverside United States Center for Embedded Computer Systems UC Irvine United States Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)9781605584706

We conducted a study of citations of papers published between 1996 and 2006 in the CODES and ISSS conferences, representing the hardware/software codesign and system synthesis community. Citations, meaning non-self-citations only, were considered from all papers known to Google Scholar, as well as only from subsequent CODES/ISSS papers. We list the most-cited CODES/ISSS papers of each year, summarizing their topics, and discussing common features of those papers. For comparison purposes, we also measured citations for the computer architecture community's ISCA and MICRO conferences, and for the field-programmable gate array community's FPGA and FCCM conferences. We point out several interesting differences among the citation patterns of the three communities. Copyright 2008 ACM.

关键词： Computer architecture

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Efficient Design Space Exploration by Knowledge Transfer 16

Efficient Design Space Exploration by Knowledge Transfer

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Li, Dandan Wang, Senzhang Yao, Shuzhen Liu, Yu-Hang Cheng, Yuanqi Sun, Xian-He Beihang Univ Sch Comp Sci & Engn Beijing Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Comp Sci & Technol Nanjing Jiangsu Peoples R China Collaborat Innovat Ctr Novel Software Technol & I Nanjing Jiangsu Peoples R China Chinese Acad Sci Inst Comp Technol Beijing Peoples R China IIT Dept Comp Sci Chicago IL 60616 USA

ISBN: (纸本)9781450344838

Due to the exponentially increasing size of design space of microprocessors and time-consuming simulations, predictive models have been widely employed in design space exploration (DSE). Traditional approaches mostly build a program-specific predictor that needs a large number of program-specific samples. Thus considerable simulation cost is required for each program. In this paper, we study the novel problem of transferring knowledge from the labeled samples of previous programs to help predict the responses of the new target program whose labeled samples are very sparse. Inspired by the recent advances of transfer learning, we propose a transfer learning based DSE framework TrDSE to build a more efficient and effective predictive model for the target program with only a few simulations by borrowing knowledge from previous programs. Specifically, TrDSE includes two phases: 1) clustering the programs based on the proposed orthogonal array sampling and the distribution related features, and 2) with the guidance of clustering results, predicting the responses of configurations in design space of the target program by a transfer learning based regression algorithm. We evaluate the proposed TrDSE on the benchmarks of SPEC CPU 2006 suite. The results demonstrate that the proposed framework is more efficient and effective than state-of-art DSE techniques.

关键词： Design space exploration Processor design Knowledge transfer

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A low-cost and low-power multi-standard video encoder

A low-cost and low-power multi-standard video encoder

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Llopis, RP Sethuraman, R Pinto, CA Peters, H Maul, S Oosterhuis, M Philips Res Labs NL-5656 AA Eindhoven Netherlands

ISBN: (纸本)1581137427

Video encoders are an important IP block in mobile multimedia systems. In this paper, we describe a low-cost low-power multi-standard (MPEG4, JPEG, and H.263) video/image encoder. The low-cost and low-power aspects are achieved by the right choice of algorithms and architectures. In the algorithm front, an embedded compression technique for reducing the size of loop memory has enabled a single-chip low-cost realization of the encoder. In the architectural front, an efficient hardware-software partitioning has contributed to the design of a low-power encoder. Further, the hardware components that accelerate the kernels of encoding are implemented as application specific instruction-set processors (ASIPs) thereby providing flexibility to address multi-standard encoding. The power and area estimates for the encoder for QCIF@15fps in 0.18mum CMOS technology are 30mW and 20mm(2) respectively including the loop memory.

关键词： video encoder multi-standard low-power low-cost ASIPs hardware/software partitioning

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