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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"
853 条 记 录,以下是121-130 订阅
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ESWEEK 2019 conference Report
ESWEEK 2019 Conference Report
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作者: Eles, Petru Mitra, Tulika Linköping University Sweden Department of Computer Science National University of Singapore Singapore Singapore
Embedded systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent, and connected computing systems. By bringing together three leading conferences [the Int... 详细信息
来源: 评论
FPGA HW/SW codesign approach for real-time image processing using HLS  1
FPGA HW/SW codesign approach for real-time image processing ...
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1st international conference on Communications, Control systems and Signal Processing, CCSSP 2020
作者: Azzaz, Mohamed Salah Maali, Abdelmadjd Kaibou, Redouane Kakouche, Ibrahim Saad, Mohamed Hamil, Hocine Ecole Militaire Polytechnique Laboratoire SEN Algiers Algeria Mouloud Mammeri University LAMPA Laboratory Tizi-Ouzou15000 Algeria
Real-time constraint is one of the most common challenges found in many critical embedded applications, namely image and video processing. However, software tools such as Matlab and general purpose microprocessor are ... 详细信息
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A New hardware Trojan Design: Distinguishing Between Trigger Inputs and Functional Inputs Is Difficult: Work-in-Progress
A New Hardware Trojan Design: Distinguishing Between Trigger...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Ge, Minghui Zhang, Ying Li, Sen Yao, Jiaqi Mao, Zhiming Chen, Xin Nanjing Univ Aeronaut & Astronaut NUAA Dept Elect & Informat Engn EIE Nanjing Peoples R China
In this paper, we propose a new hardware Trojan Design. This design makes all HT trigger inputs have the same impact as functional inputs on output signals. It is difficult to distinguish between trigger inputs and fu... 详细信息
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Work-in-Progress: Fine-Grained Acceleration using Runtime Integrated Custom Execution (RICE)
Work-in-Progress: Fine-Grained Acceleration using Runtime In...
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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)
作者: Pakanati, Leela McMichen, John T. Estrada, Zachary Rose Hulman Inst Technol Terre Haute IN 47803 USA
Runtime Integrated Custom Execution (RICE) relocates traditional peripheral reconfigurable acceleration devices into the pipeline of the processor. This relocation unlocks fine-grained acceleration previously impeded ... 详细信息
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Techniques for Design Analysis and Modification Based on ASAP Model Work-in-Progress
Techniques for Design Analysis and Modification Based on ASA...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Du, Ke Domas, Stephane Lenczner, Michel Univ Bourgogne Franche Comte FEMTO ST Inst UMR 6174 CNRS Belfort France
In the domain of model-based design, the main challenge is to provide a model with a set of conditions and algorithms to ensure that the designed system produces correct results. A dataflow based model called Actors w... 详细信息
来源: 评论
Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Progress
Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Pro...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Gong, Zicheng Jiang, Wei Zhan, Jinyu Song, Ziwei Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China
With increasing applications of Deep Neural Networks (DNNs) to edge computing systems, security issues have received more attentions. Particularly, model stealing attack is one of the biggest challenge to the privacy ... 详细信息
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Attention-Based Secure Feature Extraction in Near Sensor Processing: Work-in-Progress
Attention-Based Secure Feature Extraction in Near Sensor Pro...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Bhowmik, Pankaj Pantho, Md Jubaer Hossain Saha, Sujan Kumar Bobda, Christophe Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA
This paper presents a secure hardware architecture of an image sensor to accelerate feature extraction using region-level parallelism. For each logical region, the design includes a region processing unit (RPU) with a... 详细信息
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Work-in-Progress: Offloading Cache Configuration Prediction to an FPGA for hardware Speedup and Overhead Reduction
Work-in-Progress: Offloading Cache Configuration Prediction ...
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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)
作者: Vazquez, Ruben Gordon-Ross, Ann Stitt, Greg Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA
In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of th... 详细信息
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Formal Verification of GCSE in the Scheduling of High-level synthesis: Work-in-Progress
Formal Verification of GCSE in the Scheduling of High-level ...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Hu, Jian Hu, Yongyang Yu, Long Wang, Wentao Yang, Haitao Kang, Yun Cheng, Jie Natl Univ Def Technol Res Inst 63 Nanjing Peoples R China Natl Univ Def Technol Coll Comp Sci & Technol Changsha Peoples R China
High-level synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/systemC) into a register-transfer level (RTL) implementation. However,... 详细信息
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Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress
Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks:...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: He, Zhiyuan Jiang, Wei Zhan, Jinyu Wang, Xupeng We, Xiangyu Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China
It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promisi... 详细信息
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