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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

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ESWEEK 2019 conference Report

ESWEEK 2019 Conference Report

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作者： Eles, Petru Mitra, Tulika Linköping University Sweden Department of Computer Science National University of Singapore Singapore Singapore

Embedded systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent, and connected computing systems. By bringing together three leading conferences [the international conference on Compilers, Architecture, and synthesis for Embedded systems (CASES), the international conference on hardware/software codesign and system synthesis (CODES+ISSS), and the international conference on Embedded software (EMSOFT)], a special Internet of Medical Things (IoMT) day, a symposium [the international Symposium on Networks-on-Chip (NOCS)], and hottopic workshops and tutorials, ESWEEK presents the attendees with a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs. © 2013 IEEE.

关键词： Embedded systems

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FPGA HW/SW codesign approach for real-time image processing using HLS 1

FPGA HW/SW codesign approach for real-time image processing ...

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1st international conference on Communications, Control systems and Signal Processing, CCSSP 2020

作者： Azzaz, Mohamed Salah Maali, Abdelmadjd Kaibou, Redouane Kakouche, Ibrahim Saad, Mohamed Hamil, Hocine Ecole Militaire Polytechnique Laboratoire SEN Algiers Algeria Mouloud Mammeri University LAMPA Laboratory Tizi-Ouzou15000 Algeria

ISBN: (纸本)9781728158358

Real-time constraint is one of the most common challenges found in many critical embedded applications, namely image and video processing. However, software tools such as Matlab and general purpose microprocessor are not suitable for deals with such a problem. Recently, FPGA reconfigurable circuit with its HLS software tools is become a very promising technology to be widely used in many applications encompassing all aspects and requirements of embedded system. This paper presents the implementation of morphological image operation including dilation, erosion and linear filtering. The implementation method is based on hardware/software (HW/SW) codesign approach using High Level synthesis (HLS) tools, Xilinx Vivado 15.2 and SDK 15.2. Zedboard FPGA platform with Zynq device is used for this work in which is connected to a PC through an Ethernet link. Captured image by Webcam is transmitted to the FPGA for processing and will be then returned to the PC to be displayed on the IHM interface, in real-time. Experimental results demonstrate the feasibility of the proposed approach and it can be extended for other applications. © 2020 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A New hardware Trojan Design: Distinguishing Between Trigger Inputs and Functional Inputs Is Difficult: Work-in-Progress

A New Hardware Trojan Design: Distinguishing Between Trigger...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Ge, Minghui Zhang, Ying Li, Sen Yao, Jiaqi Mao, Zhiming Chen, Xin Nanjing Univ Aeronaut & Astronaut NUAA Dept Elect & Informat Engn EIE Nanjing Peoples R China

ISBN: (纸本)9781728191980

In this paper, we propose a new hardware Trojan Design. This design makes all HT trigger inputs have the same impact as functional inputs on output signals. It is difficult to distinguish between trigger inputs and functional inputs. Simultaneously, trigger inputs will not be identified as redundant inputs. This approach can defeat the existing detection methods which identify weakly affecting and red Cant trigger inputs across multiple sequential levels. The proposed HT has stealthiness and general applicability.

关键词： hardware trojan trigger inputs functional inputs

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Work-in-Progress: Fine-Grained Acceleration using Runtime Integrated Custom Execution (RICE)

Work-in-Progress: Fine-Grained Acceleration using Runtime In...

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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Pakanati, Leela McMichen, John T. Estrada, Zachary Rose Hulman Inst Technol Terre Haute IN 47803 USA

ISBN: (纸本)9781450369251

Runtime Integrated Custom Execution (RICE) relocates traditional peripheral reconfigurable acceleration devices into the pipeline of the processor. This relocation unlocks fine-grained acceleration previously impeded by communication overhead to a peripheral accelerator. Preliminary simulation results on a subset of the PARSEC benchmark suite shows promise for RICE in HPC applications.

关键词： RISC-V hardware Acceleration FPGA hardware-software Co-Design Gem5 PARSEC

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Techniques for Design Analysis and Modification Based on ASAP Model Work-in-Progress

Techniques for Design Analysis and Modification Based on ASA...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Du, Ke Domas, Stephane Lenczner, Michel Univ Bourgogne Franche Comte FEMTO ST Inst UMR 6174 CNRS Belfort France

ISBN: (纸本)9781728191980

In the domain of model-based design, the main challenge is to provide a model with a set of conditions and algorithms to ensure that the designed system produces correct results. A dataflow based model called Actors with Stretchable Access Patterns (ASAP) has been recently proposed, which takes the behavior of functional blocks on real architectures, especially FPGAs, into account. In this work, we present the framework of techniques to analyze the correctness of designs based on the ASAP model and to determine a set of modifications that must be applied to faulty cases to ensure the conformance of all actors. The principles are illustrated by a realistic application.

关键词： ASAP FPGA model-based design system analysis EDA

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Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Progress

Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Pro...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Gong, Zicheng Jiang, Wei Zhan, Jinyu Song, Ziwei Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China

ISBN: (纸本)9781728191980

With increasing applications of Deep Neural Networks (DNNs) to edge computing systems, security issues have received more attentions. Particularly, model stealing attack is one of the biggest challenge to the privacy of models. To defend against model stealing attack, we propose a novel protection architecture with fuzzy models. Each fuzzy model is designed to generale wrong predictions corresponding to a particular category. In addition, we design a special voting strategy to eliminate the systemic errors, which can destroy the dark knowledge in predictions at the same time. Preliminary experiments show that our method substantially decreases the clone model's accuracy (up to 20%) without loss of inference accuracy for benign users.

关键词： Deep neural networks

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Attention-Based Secure Feature Extraction in Near Sensor Processing: Work-in-Progress

Attention-Based Secure Feature Extraction in Near Sensor Pro...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Bhowmik, Pankaj Pantho, Md Jubaer Hossain Saha, Sujan Kumar Bobda, Christophe Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

ISBN: (纸本)9781728191980

This paper presents a secure hardware architecture of an image sensor to accelerate feature extraction using region-level parallelism. For each logical region, the design includes a region processing unit (RPU) with an attention module (AM). The AM activates the processing in the RPU if there are no spatiotemporal redundancies. It reduces power consumption and data volume by utilizing the concepts of predictive coding. Also, every RPU has a crypto-core driven by the AM to withstand against adversaries. Simulation results show we can save 89.70% power with a significant speedup.

关键词： Pixel Level Processing SIFT Attention Module Image Sensor hardware security FPGA ASIC

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Work-in-Progress: Offloading Cache Configuration Prediction to an FPGA for hardware Speedup and Overhead Reduction

Work-in-Progress: Offloading Cache Configuration Prediction ...

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作者： Vazquez, Ruben Gordon-Ross, Ann Stitt, Greg Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of th... 详细信息

ISBN: (纸本)9781450369237

关键词： cache configurable artificial neural network mobile devices FPGA phases machine learning

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Formal Verification of GCSE in the Scheduling of High-level synthesis: Work-in-Progress

Formal Verification of GCSE in the Scheduling of High-level ...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hu, Jian Hu, Yongyang Yu, Long Wang, Wentao Yang, Haitao Kang, Yun Cheng, Jie Natl Univ Def Technol Res Inst 63 Nanjing Peoples R China Natl Univ Def Technol Coll Comp Sci & Technol Changsha Peoples R China

ISBN: (纸本)9781728191980

High-level synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/systemC) into a register-transfer level (RTL) implementation. However, an error may exist in the RTL implementation from the compiler in the high-level synthesis due to the complex and error prone compiling process. Global common subexpression elimination (GCSE) is a commonly used code motion technique in the scheduling of high-level synthesis. In this paper, we present an equivalence checking method to verify GCSE in the scheduling of high-level synthesis by enhancing the path equivalence criteria. The initial experimental results demonstrate our method can indeed verify the GCSE which has not been properly addressed in the past.

关键词： Equivalence Checking High-level synthesis FSMD Global Common Subexpression Elimination

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Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress

Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks:...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： He, Zhiyuan Jiang, Wei Zhan, Jinyu Wang, Xupeng We, Xiangyu Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China

ISBN: (纸本)9781728191980

It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promising result, which however suffers from a high computation cost. In this paper, we design a new heatmap-aware method to defend adversarial attacks, leading to a significant decrease in the time cost. To he specific, we compute the classification importance from each part of the input to obtain the heatmap of the data, and the key areas of classification are extracted according to the heatmap. A series of transformations are applied to the key areas of the classification, which reduces the amount of data to be processed and thus reduces the time cost. A set of preliminary experiments are conducted to testify the effectiveness of the proposed approach.

关键词： Costs

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