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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 852 条记录，以下是131-140 订阅

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A Case of system-level hardware/software Co-design and Co-verification of a Commodity Multi-Processor system with Custom hardware 12

A Case of System-level Hardware/Software Co-design and Co-ve...

引用

10th ACM international conference on hardware/software-codesign and system synthesis

作者： Hong, Sungpack Oguntebi, Tayo Casper, Jared Bronson, Nathan Kozyrakis, Christos Olukotun, Kunle Oracle Labs Belmont USA Stanford University Palo Alto USA

ISBN: (纸本)9781450314268

This paper presents an interesting system-level co-design and co-verification case study for a non-trivial design where multiple high-performing x86 processors and custom hardware were connected through a coherent interconnection fabric. In functional verification of such a system, we used a processor bus functional model (BFM) to combine native software execution with a cycle-accurate interconnect simulator and an HDL simulator. However, we found that significant extensions need to be made to the conventional BFM methodology in order to capture various data-race cases in simulation, which eventually happen in modern multi-processor systems. Especially essential were faithful imp lementations of the memory consistency model and cache coherence protocol, as well as timing randomization. We demonstrate how such a co-simulation environment can be constructed from existing tools and software. Lessons from our study can similarly be applied to design and verification of other tightly-coupled systems.

关键词： Co-Verification Co-Simulation Bus Functional Model FPGA Prototyping Transactional Memory

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The Shift to Multicores in Real-Time and Safety-Critical systems

The Shift to Multicores in Real-Time and Safety-Critical Sys...

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Saidi, Selina Ernst, Rolf Uhrig, Sascha Theiling, Henrik de Dinechin, Benoit Dupont Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Airbus Grp Innovat Leiden Netherlands SYSGO AG Mainz Germany Kalray SA Montbonnot St Martin France

ISBN: (纸本)9781467383219

In real-time and safety-critical systems, the move towards multicores is becoming unavoidable in order to keep pace with the increasing required processing power and to meet the high integration trend while maintaining a reasonable power consumption. However, standard multicore systems are mainly designed to increase average performance, whereas embedded systems have additional requirements with respect to safety, reliability and realtime behavior. Therefore, the shift to multicores raises several challenges the embedded community has to face. These challenges involve the design of certifiable multicore platforms, the management of shared resources and the development/integration of parallel software. These issues are encountered at different steps of system development, from modeling and design to software implementation and hardware deployment. Therefore, both multicore/semiconductor manufacturers and the real-time community have to bridge the gap in order to meet the challenges imposed by multicores. The goal of this paper is to trigger such a discussion as an attempt to bridge the gap between the two worlds and to raise awareness about the hurdles and challenges that need to be tackled.

关键词： embedded systems parallel processing power aware computing resource allocation safety-critical software certifiable multicore platform design hardware deployment multicore systems parallel software development parallel software integration real-time system safety-critical system shared resource management software implementation system development Aerospace electronics hardware Multicore processing Real-time systems Safety software Timing safety-critical software real-time systems Embedded systems power aware computing software implementation avionics systems development computer software management of resources Computer hardware PARALLEL PROCESSING (COMPUTERS) Resource utilization Consumer safety safety software design

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Flattening-based Mapping of Imperfect Loop Nests for CGRAs 14

Flattening-based Mapping of Imperfect Loop Nests for CGRAs

引用

international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Lee, Jongeun Seo, Seongseok Lee, Hongsik Sim, Hyeon Uk UNIST Sch ECE Ulsan South Korea

ISBN: (纸本)9781450330510

For loop accelerators such as coarse-grained reconfigurable architectures (CGRAs) and GP-GPUs, nested loops represent an important source of parallelism. Existing solutions to mapping nested loops on CGRAs, however, are either designed for perfectly nested loops only, or expensive and inflexible. Efficient CGRA mapping of imperfect loops with arbitrary nesting depth still remains a challenge. In this paper we propose a compiler-hardware co-operative approach that is flexible and yet able to generate efficient mappings for imperfect nested loops. It is based on loop flattening, but to mitigate the negative impact of flattening we combine loop fission and a light-weight architecture extension that is designed to accelerate common operation patterns appearing frequently in flattened loops. Our experimental results using imperfect loops from multimedia and DSP domains demonstrate that our special operations can cover a large portion of nested loop operations, improve performance of nested loops by nearly 30% over using loop flattening only, and achieve near-ideal executions on CGRAs for imperfect loops.

关键词： parallel processing program compilers program control structures CGRA DSP domains GP-GPUs coarse-grained reconfigurable architectures compiler-hardware cooperative approach flattening-based loop nest mapping light-weight architecture extension loop accelerators loop fission loop flattening multimedia domains nested loop mapping parallelism source Arrays Kernel Nickel Pipeline processing Registers Coarse-grained Reconfigurable Architecture Loops program control structures Imperfect Pipeline processing compilers Registers PARALLEL PROCESSING (COMPUTERS) Nickel Contraceptive Coil FLATTENING Kernel MAPPING(MATHEMATICAL)

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SPI-SNOOPER: A hardware-software Approach for Transparent Network Monitoring in Wireless Sensor Networks 12

SPI-SNOOPER: A Hardware-Software Approach for Transparent Ne...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Hossain, Mohammad Sajjad Lee, Woo Suk Raghunathan, Vijay Google Inc Mountain View CA USA Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9781450314268

The lack of post-deployment visibility into system operation is one of the major challenges in ensuring reliable operation of remotely-deployed embedded systems such as wireless sensor nodes. Over the years, many software-based solutions (in the form of debugging tools and protocols) have been proposed for in-situ system monitoring. However, all of them share the trait that the monitoring functionality is implemented as software executing on the same embedded processor that the main application executes on. This is a poor design choice from a reliability perspective. This paper makes the case for a joint hardware-software solution to this problem and advocates the use of a dedicated reliability co-processor that is tasked with monitoring the operation of the embedded system. As an embodiment of this design principle, this paper presents SPI-SNOOPER, a co-processor augmented hardware platform specifically designed for network monitoring. SPI-SNOOPER is completely cross-compatible with the TELOS wireless sensor nodes from an operational standpoint and is based on a novel hardware architecture that enables transparent snooping of the communication bus between the main processor and the radio of the wireless embedded system. The accompanying software architecture provides a powerful tool for monitoring, logging, and even controlling all the communication that takes place between the main processor and the radio. We present a rigorous evaluation of our prototype and demonstrate its utility using a variety of usage scenarios.

关键词： Wireless sensor networks reliability hardware-software co-design co-processor monitoring snooping

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Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip

Bus architecture synthesis for hardware-software co-design o...

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21st international conference on Computer Design

作者： Thepayasuwan, N Damle, V Doboli, A SUNY Stony Brook Dept Elect & Comp Engn Stony Brook NY 11794 USA

ISBN: (纸本)0769520251

system level design always has a disadvantage of not possessing detailed knowledge of the communication sub-system. This is a crucial issue for system-on-Chip design, where uncertainty in communication by very deep submicron effects cannot be neglected. This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The algorithm is part of a hardware-software codesign methodology for resource constrained embedded applications. BA synthesis includes finding the bus topology, and routing the individual buses so that various constraints, like bus length, topology complexity, potential for communication conflicts over time, are addressed. The paper presents BA synthesis results for a network processor, and a JPEG SoC.

关键词： Integrated circuit layout

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synthesis of Real-Time Embedded software with Local and Global Deadlines 03

Synthesis of Real-Time Embedded Software with Local and Glob...

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First IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003

作者： Hsiung, Pao-Ann Lin, Cheng-Yi Department of Computer Science National Chung Cheng University Chiayi-621 Taiwan

ISBN: (纸本)1581137427

Current methods cannot synthesize real-time embedded software applications when the global deadline of a task is shorter than the total of all local deadlines along a critical path in the task. This creates unnecessary modeling limitations which directly affect the types of systems synthesizable. We propose a quasi-dynamic scheduling algorithm for simultaneously guaranteeing both local and global deadlines, while satisfying all precedence constraints among sub-tasks and among tasks. Through this scheduling procedure, we are able to formally synthesize real-time embedded software from a network of Real-Time Petri Nets specification. Application examples, including a driver for the Master/Slave role switch in Bluetooth wireless communication devices, are given to illustrate the feasibility of the scheduling algorithm.

关键词： Embedded systems

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You can catch more bugs with transaction level honey 08

You can catch more bugs with transaction level honey

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Abramovici, Miron Goossens, Kees Vermeulen, Bart Greenbaum, Jack Stollon, Neal Donlin, Adam DAFCA NXP Greenhills Software United States HDL Dynamics Xilinx Research

ISBN: (纸本)9781605584706

In this special session we explore holistic approaches to hardware/software debug that use or integrate transaction level models (TLMs). We present several TLM-based approaches to system-level diagnostics, ranging from use of most popular transaction level modeling languages through to hybrid technologies that combine TLMs with other well known diagnostic tools like in-silicon trace logic. Copyright 2008 ACM.

关键词： Modeling languages

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The challenges of embedded system design

The challenges of embedded system design

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3rd IEEE/ACM/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Muller, Mike ARM

ISBN: (纸本)1595931619

As complexity grows the importance of system level exploration, design, verification and debug becomes inescapable. However while there has been great progress in process technology, tools and methodologies resulting in ever more sophisticated platforms some of the critical design parameters have been moving in the wrong direction. Power is becoming a critical challenge that will require new solutions for both design and manufacturing if the roller coaster ride is to continue.

关键词： Embedded systems

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A parallelizable approach for mining likely invariants

A parallelizable approach for mining likely invariants

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Danese, Alessandro Piccolboni, Luca Pravadelli, Graziano Univ Verona Str Grazie 15 I-37134 Verona Italy

ISBN: (纸本)9781467383219

A relevant aspect in design analysis and verification is monitoring how logic relations among different variables change at run time. Current static approaches suffer from scalability problems that prevent their adoption on large designs. On the contrary, dynamic techniques scale better from the memory-consumption point of view. However, to achieve a high accuracy, they require to analyse a huge number of ( long) execution traces, which results in time-consuming phases. In this paper, we present a new efficient approach to automatically infer logic relations among the variables of a design implementation. Both a sequential and a GPU-oriented parallel implementation are proposed to dynamically extract likely invariants from execution traces on different time windows. Execution traces composed of millions of simulation instants can be efficiently analysed.

关键词： data mining graphics processing units hardware-software codesign GPU-oriented parallel implementation design analysis design verification dynamic techniques execution traces likely invariants mining logic relations memory-consumption view point parallelizable approach scalability problems sequential parallel implementation static approaches time windows time-consuming phases Accuracy Analytical models Computer architecture Engines Graphics processing units Instruction sets Instruments design analysis instruction sets design verification Time windows hardware/software co-design Computer Architecture Graphics Processing Unit Engines ANALYSIS MODELS data mining Legal Executions time phase Invariant

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HW/SW auto-coupling for fast IP integration in SoC designs

HW/SW auto-coupling for fast IP integration in SoC designs

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5th international conference on Embedded software and systems

作者： Hwang, Yin-Tsung Chen, Jun-Yen Chiu, Jun-Jieh Natl Chung Hsing Univ Dept Elect Engn Taichung 40201 Taiwan

ISBN: (纸本)9780769532875

IP intergration in SoC nowadays contains two design aspects, i.e. hardware interface and software driver. The hardware interface supports necessary signal mapping, protocol translation and data buffering so that an IP can adapt to various system architectures. The software driver provides IP access controls from the software domain in the presence of operating system. The automation of both design processes in a coupling manner is addressed in this paper. We first outline the methodology of automatic interface synthesis and elaborate on the topics of signal mapping, protocol conversion and interface template architecture. We next present the framework of a baseline driver generator and detail the generation schemes of basic file operations and other functions and driver settings. Both tools are linked to form a HW/SW auto-coupling design suite, which features minimum user knowledge toward the hardware and OS details in usage. Some design examples on the interface synthesis tool and an JPEG codec HW/SW codesign example on the integrated design suite are provided to prove the effectiveness of the proposed system.

关键词： system-on-chip

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