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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 853 条记录，以下是141-150 订阅

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Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy for Blockchain Storage systems: Work-in-Progress

Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Jing Liao Zhengda Li Yi Wang College of Computer Science and Software Engineering The National Engineering Laboratory for Big Data System Computing Technology Shenzhen University Shenzhen China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

Current LSM-Tree-based blockchain storage system will assign the data from multiple system users to the same disk drive. This will lead to the inefficient usage of physical spaces in disk and cause extra compaction operations for LSM - Tree. This paper presents Meta-Chain , a user-aware cross-layer space allocation strategy for blockchain storage systems. As a cross-layer design, Meta-Chain redesigns the organization of LSM - Tree and utilizes the rich functionalities provided by open-channel SSD. Experimental results show that Meta-Chain can effectively reduce write amplification and extend the lifetime of SSD in comparison with representative schemes.

关键词： Disk drives Blockchain Organizations Compaction Resource management

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WiderFrame: An Automatic Customization Framework for Building CNN Accelerators on FPGAs: Work-in-Progress

WiderFrame: An Automatic Customization Framework for Buildin...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Gong, Lei Wang, Chao Li, Xi Zhou, Xuehai Univ Sci & Technol China Sch Comp Sci & Technol Hefei Peoples R China

ISBN: (纸本)9781728191980

hardware acceleration based on FPGA has been an important means to improve the computational efficiency of CNNs. However, due to the increasing complexity of the modern CNNs and the diversity of neural computing engines, it is challenging to make full use of FPGAs' customizability for efficient and fast accelerator designs. This paper proposes Wider-Frame, an automatic customization framework for building CNN accelerators on FPGA. Towards fully exploiting the customizability of FPGA for specific computing scenarios, WiderFrame integrates a systematical design space exploration methodology considered with different parallel and data reuse manners among various neural computing engines, a parameterized configurable code template with a set of macro instruction mechanism, for automatically generating the underlying hardware units and the control flow. Evaluation results show that WiderFrame can well support more CNN types, and can improve the performance and the energy efficiency up to 1.25x and 1.68x compared with state-of-the-art frameworks.

关键词： FPGA CNN hardware accelerator Framework

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Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress

Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks:...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Zhiyuan He Wei Jiang Jinyu Zhan Xupeng Wang Xiangyu Wen School of Information & Software Engineering University of Electronic Science & Technology of China China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promising result, which however suffers from a high computation cost. In this paper, we design a new heatmap-aware method to defend adversarial attacks, leading to a significant decrease in the time cost. To be specific, we compute the classification importance from each part of the input to obtain the heatmap of the data, and the key areas of classification are extracted according to the heatmap. A series of transformations are applied to the key areas of the classification, which reduces the amount of data to be processed and thus reduces the time cost. A set of preliminary experiments are conducted to testify the effectiveness of the proposed approach.

关键词： Heating systems Resists Data mining Task analysis

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Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Progress

Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Pro...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Zicheng Gong Wei Jiang Jinyu Zhan Ziwei Song School of Information & Software Engineering University of Electronic Science & Technology of China China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

With increasing applications of Deep Neural Networks (DNNs) to edge computing systems, security issues have received more attentions. Particularly, model stealing attack is one of the biggest challenge to the privacy of models. To defend against model stealing attack, we propose a novel protection architecture with fuzzy models. Each fuzzy model is designed to generate wrong predictions corresponding to a particular category. In addition' we design a special voting strategy to eliminate the systemic errors, which can destroy the dark knowledge in predictions at the same time. Preliminary experiments show that our method substantially decreases the clone model's accuracy (up to 20%) without loss of inference accuracy for benign users.

关键词： Privacy Computational modeling Neural networks Computer architecture Predictive models Security Edge computing

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Work-in-Progress: A concept of a hardware design environment with the functional language Elixir

Work-in-Progress: A concept of a hardware design environment...

引用

Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Takase, Hideki Matsui, Kentaro Ueno, Yoshihiro Mori, Masakazu Hisae, Yuki Yamazaki, Susumu Kyoto Univ Sakyo Ku Kyoto Japan Delight Syst Co Ltd Chuo Ku Fukuoka Japan Karabiner Technol Inc Chuo Ku Fukuoka Japan Univ Kitakyushu Wakamatsu Ku Kitakushu Japan JST PRESTO Tokyo Japan

ISBN: (纸本)9781450369237

The functional language Elixir is designed to be effective for the application. One of the most considerable feature of Elixir is that it is easy to realize the parallel processing with the standard library, such as Flow. In this paper, we study a design environment for hardware circuits using Elixir as a design language. We propose a synthesize flow for data flow hardware on the FPGA from the native Elixir code. Our method synthesizes functional equivalence circuits from the description of Enum and Flow in Elixir, which are libraries for direct manipulation and parallel processing of data collection in Elixir. Data flow is implemented base on the pipeline operator vertical bar> which connects the processing relation of the function by the data processing order. To realize a hardware design environment by Elixir, this paper shares current status of our implementation.

关键词： Elixir functional language high-level synthesis

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RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress

RePAiR: A Strategy for Reducing Peak Temperature while Maxim...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Shounak Chakraborty Sangeet Saha Magnus Sjalander Klaus McDonald-Maier Norwegian University of Science and Technology (NTNU) Trondheim Norway Embedded and Intelligent Systems Laboratory University of Essex Colchetser UK

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

Improving accuracy in approximate real-time computing without violating thermal-energy constraints of the underlying hardware is a challenging problem. The execution of approximate real-time tasks can individually be bifurcated into two components: (i) execution of the mandatory part of the task to obtain a result of acceptable quality, followed by (ii) partial/complete execution of the optional part, which refines the initially obtained result, to increase the accuracy without violating the temporal-deadline. This paper introduces RePAiR, a novel task-allocation strategy for approximate real-time applications, combined with fine-grained DVFS and on-line task migration of the cores and power-gating of the last level cache, to reduce chip-temperature while respecting both deadline and thermal constraints. Furthermore, gained thermal benefits can be traded against system-level accuracy by extending the execution-time of the optional part.

关键词： Maintenance engineering Real-time systems hardware Task analysis

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Accelerating Queries of MongoDB by an FPGA-based Storage Engine: Work-in-Progress

Accelerating Queries of MongoDB by an FPGA-based Storage Eng...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Jinyu Zhan Junting Wu Wei Jiang Ying Li Jianping Zhu School of Information & Software Engineering University of Electronic Science & Technology of China China Tencent Technology Shenzhen Company Ltd China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

In this paper, we propose a storage engine for MongoDB to accelerate the queries and reduce the memory usage. An FPGA-based query accelerator is deployed to speed up the queries while hot data is migrated from memory to SSD to reduce memory occupancy by our storage engine. Moreover, multiple query tasks of MongoDB are performed in parallel and query conditions are parameterized to support diversified queries. Based on TPC- H benchmark and Tencent data set, experimental results demonstrate that our storage engine can achieve higher query efficiency (saving up to 63.5 % time overhead) and lower memory occupancy (reducing up to 73.4 % memory usage) compared with traditional MongoDB.

关键词： Memory management Benchmark testing Acceleration Task analysis Engines Field programmable gate arrays

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Work-in-Progress: PowerMonitor: Design Pattern for Modelling Energy-Aware Embedded systems

Work-in-Progress: PowerMonitor: Design Pattern for Modelling...

引用

作者： Uelschen, Michael Schaarschmidt, Marco Fuhrmann, Christian Westerkamp, Clemens Univ Appl Sci Osnabruck Fac Engn & Comp Sci Osnabruck Germany

ISBN: (纸本)9781450369244

This paper introduces a new software design pattern that can be applied to embedded systems. The pattern enables the application to access the peripheral devices under defined power conditions and allows to implement a fine-grained and energy-efficient strategy on using functional units of the microcontroller. The approach considers power consumption properties of the CPU itself as well as properties of external peripheral devices like connected sensors and actuators.

关键词： software Architecture Design Patterns Embedded systems Energy efficiency Template Meta Programming

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An ESL Methodology for HW/SW Co-Design of Monitorable Embedded systems: the “Design for Monitorability” Project - Work-in-Progress

An ESL Methodology for HW/SW Co-Design of Monitorable Embedd...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Giacomo Valente Tania Di Mascio Luigi Pomante Vincenzo Stoico DISIM/DEWS Università degli Studi dell'Aquila ITALY

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

This paper proposes an Electronic system-Level (ESL) Methodology for HW/SW Co-Design of Monitorable Embedded systems. In particular, this paper aims to define an innovative topic called Design for Monitorability (DfM). DfM exploits ESL HW/SW co-design techniques to satisfy Monitorability Requirements (M_REQs) by considering them since the initial steps of the HW/SW co-design flow as additional ones. DfM has the final goal of suggesting to the designer an On-Chip Monitoring system (OCMS) able to satisfy M _ REQs., to be integrated in the final system (i.e., possibly heterogeneous and/or parallel SoCs) while still respecting the other possible nonfunctional requirements imposed to the system implementation (e.g., execution time, area/resource utilization, energy consumption, etc.). The description of the motivations and the main concepts behind the proposed methodology represent the core of the paper.

关键词： Energy consumption Embedded systems system-on-chip Monitoring system implementation

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WiderFrame: An Automatic Customization Framework for Building CNN Accelerators on FPGAs: Work-in-Progress

WiderFrame: An Automatic Customization Framework for Buildin...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Lei Gong Chao Wang Xi Li Xuehai Zhou School of Computer Science and Technology University of Science and Technology of China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

hardware acceleration based on FPGA has been an important means to improve the computational efficiency of CNNs. However, due to the increasing complexity of the modern CNNs and the diversity of neural computing engines, it is challenging to make full use of FPGAs' customizability for efficient and fast accelerator designs. This paper proposes Wider-Frame, an automatic customization framework for building CNN accelerators on FPGA. Towards fully exploiting the customiz-ability of FPGA for specific computing scenarios, WiderFrame integrates a systematical design space exploration methodology considered with different parallel and data reuse manners among various neural computing engines, a parameterized configurable code template with a set of macro instruction mechanism, for automatically generating the underlying hardware units and the control flow. Evaluation results show that WiderFrame can well support more CNN types, and can improve the performance and the energy efficiency up to 1.25 x and 1.68 x compared with state-of-the-art frameworks.

关键词： Design methodology Buildings Energy efficiency Space exploration Field programmable gate arrays Engines hardware acceleration

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