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Aggressive Energy Reduction for Video Inference with software-only Strategies

ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 1–20页

作者： Goncalves, Larissa Rozales De Moura, Rafael Fao Carro, Luigi Univ Fed Rio Grande do Sul Porto Alegre RS Brazil

In the past years, several works have proposed custom hardware and software-based techniques for the acceleration of Convolutional Neural Networks (CNNs). Most of these works focus on saving computations by changing the used precision or modifying frame processing. To reach a more aggressive energy reduction, in this paper we propose software-only modifications to the CNNs inference process. Our approach exploits the inherent locality in videos by replacing entire frame computations with a movement prediction algorithm. Furthermore, when a frame must be processed, we avoid energy-demanding floating-point operations, and at the same time reduce memory accesses by employing look-up tables in place of the original convolutions. Using the proposed approach, one can reach significant energy gains of more than 25x for security cameras, and 12x for moving vehicles applications, with only small software modifications.

关键词： Convolutional Neural Networks frame predicton computation reuse

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HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2021年第5期20卷 66-66页

作者： Fasfous, Nael Vemparala, Manoj Rohit Frickenstein, Alexander Valpreda, Emanuele Salihu, Driton Nguyen Anh Vu Doan Unger, Christian Nagaraja, Naveen Shankar Martina, Maurizio Stechele, Walter Tech Univ Munich Munich Germany BMW Autonomous Driving Munich Germany Politecn Torino Turin Italy

Model compression through quantization is commonly applied to convolutional neural networks (CNNs) deployed on compute and memory-constrained embedded platforms. Different layers of the CNN can have varying degrees of numerical precision for both weights and activations, resulting in a large search space. Together with the hardware (HW) design space, the challenge of finding the globally optimal HW-CNN combination for a given application becomes daunting. To this end, we propose HW-FlowQ, a systematic approach that enables the co-design of the target hardware platform and the compressed CNN model through quantization. The search space is viewed at three levels of abstraction, allowing for an iterative approach for narrowing down the solution space before reaching a high-fidelity CNN hardware modeling tool, capable of capturing the effects of mixed-precision quantization strategies on different hardware architectures (processing unit counts, memory levels, cost models, dataflows) and two types of computation engines (bit-parallel vectorized, bit-serial). To combine both worlds, a multi-objective non-dominated sorting genetic algorithm (NSGA-II) is leveraged to establish a Pareto-optimal set of quantization strategies for the target HW-metrics at each abstraction level. HW-FlowQ detects optima in a discrete search space and maximizes the task-related accuracy of the underlying CNN while minimizing hardware-related costs. The Pareto-front approach keeps the design space open to a range of non-dominated solutions before refining the design to a more detailed level of abstraction. With equivalent prediction accuracy, we improve the energy and latency by 20% and 45% respectively for ResNet56 compared to existing mixed-precision search methods.

关键词： Convolutional neural networks multi-objective optimization hardware modeling genetic algorithms quantization

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Work-in-Progress: A Neuromorphic Approach of the Sound Source Localization Task in Real-Time Embedded systems

Work-in-Progress: A Neuromorphic Approach of the Sound Sourc...

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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Gutierrez-Galan, Daniel Pedro Jimenez-Fernandez, Juan Jimenez-Fernandez, Angel Tapiador-Morales, Ricardo Rios-Navarro, Antonio Linares-Barranco, Alejandro Univ Seville Seville Spain

ISBN: (纸本)9781450369244

Autonomous robots have become a very popular topic within the artificial intelligence field. These systems are able to perform difficult or risky tasks that could be dangerous when done by humans or trained animals. Vision is commonly considered the most relevant input sensor for autonomous robots and tracking systems. However, auditory information is also important in some specific situations where vision cannot provide any useful information when navigating. In this work, a spike-based model of the medial superior olive of the inner ear has been implemented in reconfigurable hardware for performing sound source localization in real time. Future works will focus on integrating this information with vision in order to achieve a fully bio-inspired autonomous tracking system.

关键词： Neuromorphic auditory sensor FPGA binaural sound localization real-time audio processing spike-based system

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A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress

A Fast Design Space Exploration Framework for the Deep Learn...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Colucci, Alessio Marchisio, Alberto Bussolino, Beatrice Mrazek, Voitech Martina, Maurizio Masera, Guido Shafique, Muhammad Tech Univ Wien Vienna Austria Politecn Torino Turin Italy Brno Univ Technol Fac Informat Technol IT4Innovat Ctr Excellence Brno Czech Republic New York Univ Abu Dhabi Div Engn Abu Dhabi U Arab Emirates

ISBN: (纸本)9781728191980

The Capsule Networks (CapsNets) is an advanced form of Convolutional Neural Network (CNN), capable of learning spatial relations and being invariant to transformations. CapsNets requires complex matrix operations which current accelerators are not optimized for, concerning both training and inference passes. Current state-of-the-art simulators and design space exploration (DSE) tools for DNN hardware neglect the modeling of training operations, while requiring long exploration times that slow down the complete design flow. These impediments restrict the real-world applications of CapsNets (e.g., autonomous driving and robotics) as well as the further development of DNNs in life-long learning scenarios that require training on low-power embedded devices. Towards this, we present XploreDL, a novel framework to perform fast yet high-fidelity USE for both inference and training accelerators, supporting both CNNs and CapsNets operations. XploreDL enables a resource-efficient DSE for accelerators, focusing on power, area, and latency, highlighting Pareto-optimal solutions which can be a green-lit to expedite the design flow. XploreDL can reach the same fidelity as ARM's SCALE-sim, while providing 600x speedup and having a 50x lower memory-footprint. Preliminary results with a deep CapsNet model on MNIST for training accelerators show promising Pareto-optimal architectures with up to 0.4 TOPS/squared-nun and 800 fJ/op efficiency. With inference accelerators for AlexNet the Pareto-optimal solutions reach up to 1.8 TOPS/squared-mm and 200 fJ/op efficiency.

关键词： Design Space Exploration hardware Accelerator Capsule Networks Convolutional Neural Networks Training

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Will My Program Break on This Faulty Processor?: Formal Analysis of hardware Fault Activations in Concurrent Embedded software

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 1-21页

作者： Bajczi, Levente Voros, Andras Molnar, Vince Budapest Univ Technol & Econ Fault Tolerant Syst Res Grp Dept Measurement & Informat Syst POB 91 H-1521 Budapest Hungary MTA BME Lendulet Cyber Phys Syst Res Grp Budapest Hungary

Formal verification is approaching a point where it will be reliably applicable to embedded software. Even though formal verification can efficiently analyze multi-threaded applications, multi-core processors are often considered too dangerous to use in critical systems, despite the many benefits they can offer. One reason is the advanced memory consistency model of such CPUs. Nowadays, most software verifiers assume strict sequential consistency, which is also the naive view of programmers. Modernmulti-core processors, however, rarely guarantee this assumption by default. In addition, complex processor architectures may easily contain design faults. Thanks to the recent advances in hardware verification, these faults are increasingly visible and can be detected even in existing processors, giving an opportunity to compensate for the problem in software. In this paper, we propose a generic approach to consider inconsistent behavior of the hardware in the analysis of software. Our approach is based on formal methods and can be used to detect the activation of existing hardware faults on the application level and facilitate their mitigation in software. The approach relies heavily on recent results of model checking and hardware verification and offers new, integrative research directions. We propose a partial solution based on existing model checking tools to demonstrate feasibility and evaluate their performance in this context.

关键词： Fault analysis memory consistency model concurrent litmus test

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FLASH: Fast Neural Architecture Search with hardware Optimization

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2021年第5期20卷 63-63页

作者： Li, Guihong Mandal, Sumit K. Ogras, Umit Y. Marculescu, Radu Univ Texas Austin Austin TX 78712 USA Univ Wisconsin Madison WI USA

Neural architecture search (NAS) is a promising technique to design efficient and high-performance deep neural networks (DNNs). As the performance requirements of ML applications grow continuously, the hardware accelerators start playing a central role in DNN design. This trend makes NAS even more complicated and time-consuming for most real applications. This paper proposes FLASH, a very fast NAS methodology that co-optimizes the DNN accuracy and performance on a real hardware platform. As the main theoretical contribution, we first propose the NN-Degree, an analytical metric to quantify the topological characteristics of DNNs with skip connections (e.g., DenseNets, ResNets, Wide-ResNets, and MobileNets). The newly proposed NN-Degree allows us to do training-free NAS within one second and build an accuracy predictor by training as few as 25 samples out of a vast search space with more than 63 billion configurations. Second, by performing inference on the target hardware, we fine-tune and validate our analytical models to estimate the latency, area, and energy consumption of various DNN architectures while executing standard ML datasets. Third, we construct a hierarchical algorithm based on simplicial homology global optimization (SHGO) to optimize the model-architecture co-design process, while considering the area, latency, and energy consumption of the target hardware. We demonstrate that, compared to the state-of-the-art NAS approaches, our proposed hierarchical SHGO-based algorithm enables more than four orders of magnitude speedup (specifically, the execution time of the proposed algorithm is about 0.1 seconds). Finally, our experimental evaluations show that FLASH is easily transferable to different hardware architectures, thus enabling us to do NAS on a Raspberry Pi-3B processor in less than 3 seconds.

关键词： Neural networks network science hardware optimization neural architecture search model-architecture co-design resource-constrained devices

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Aggressive Energy Reduction for Video Inference with software-only Strategies

Aggressive Energy Reduction for Video Inference with Softwar...

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作者： Goncalves, Larissa Rozales De Moura, Rafael Fao Carro, Luigi Univ Fed Rio Grande do Sul Porto Alegre RS Brazil

关键词： Convolutional Neural Networks frame predicton computation reuse

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Treble: Fast software Updates by Creating an Equilibrium in an Active software Ecosystem of Globally Distributed Stakeholders

Treble: Fast Software Updates by Creating an Equilibrium in ...

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作者： Yim, Keun Soo Malchev, Iliyan Hsieh, Andrew Burke, Dave Google 1600 Amphitheatre Pkwy Mountain View CA 94043 USA

This paper presents our experience with Treble, a two-year initiative to build the modular base in Android, a Java-based mobile platform running on the Linux kernel. Our Treble architecture splits the hardware independent core framework written in Java from the hardware dependent vendor implementations (e.g., user space device drivers, vendor native libraries, and kernel written in C/C++). Cross-layer communications between them are done via versioned, stable inter-process communication interfaces whose backward compatibility is tested by using two API compliance suites. Based on this architecture, we repackage the key Android software components that suffered from crucial post-launch security bugs as separate images. That not only enables separate ownerships but also independent updates of each image by interested ecosystem entities. We discuss our experience of delivering Treble architectural changes to silicon vendors and device makers using a yearly release model. Our experiments and industry rollouts support our hypothesis that giving more freedom to all ecosystem entities and creating an equilibrium are a transformation necessary to further scale the world largest open source ecosystem with over two billion active devices.

关键词： Open source ecosystem software architecture software update

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FPGA HW/SW codesign Approach for Real-time Image Processing Using HLS

FPGA HW/SW Codesign Approach for Real-time Image Processing ...

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Communications, Control systems and Signal Processing (CCSSP), 2020 1st international conference on

作者： Mohamed Salah AZZAZ Abdelmadjd MAALI Redouane KAIBOU Ibrahim KAKOUCHE Mohamed SAAD Hocine HAMIL Ecole Militaire Polytechnique Laboratoire SEN Algiers Algeria Mouloud Mammeri University LAMPA Laboratory Tizi-Ouzou Algeria

ISBN: (数字)9781728158358

ISBN: (纸本)9781728158365

Real-time constraint is one of the most common challenges found in many critical embedded applications, namely image and video processing. However, software tools such as Matlab and general purpose microprocessor are not suitable for deals with such a problem. Recently, FPGA reconfigurable circuit with its HLS software tools is become a very promising technology to be widely used in many applications encompassing all aspects and requirements of embedded system. This paper presents the implementation of morphological image operation including dilation, erosion and linear filtering. The implementation method is based on hardware/software (HW/SW) codesign approach using High Level synthesis (HLS) tools, Xilinx Vivado 15.2 and SDK 15.2. Zedboard FPGA platform with Zynq device is used for this work in which is connected to a PC through an Ethernet link. Captured image by Webcam is transmitted to the FPGA for processing and will be then returned to the PC to be displayed on the IHM interface, in real-time. Experimental results demonstrate the feasibility of the proposed approach and it can be extended for other applications.

关键词： Field programmable gate arrays Tools IP networks Convolution hardware Real-time systems Program processors

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Work-in-Progress: Physics-Based software Analysis for Safety-Critical Embedded Applications

Work-in-Progress: Physics-Based Software Analysis for Safety...

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作者： Goettlich, Philipp Reuss, Hans-Christian ETAS GmbH Stuttgart Germany Univ Stuttgart Stuttgart Germany

ISBN: (纸本)9781450369244

Physics-based software systems are a new trend in automotive feature and control implementation. They are used for modern applications in the context of automated driving and ADAS. Implementing physical models on critical embedded targets (for example electronic control systems) causes many safety related challenges, as they are far more complex than ordinary control algorithms. The code needs to be secured appropriately. This paper proposes a new approach to include physical properties in the V&V (verification & validation) and testing process in order to analyze functional code behavior of physical systems on targets automatically. For this, physical properties are extracted from the physics-based models, compared with databases and defined as constraints in order to analyze discretizations and calculations of the code. The mass conservation law for example is very beneficial for evaluating different discretization methods of model code automatically. This way, an evaluation of the correct behavior is faster, more efficient and safety and development time of physics-based embedded application code is improved. Our approach proved to be useful in finding physics-related errors in physics-based embedded systems automatically. The generated physical constraints can be used for test data generation.

关键词： Physical properties

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