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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 853 条记录，以下是151-160 订阅

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HW/SW auto-coupling for fast IP integration in SoC designs

HW/SW auto-coupling for fast IP integration in SoC designs

引用

5th international conference on Embedded software and systems

作者： Hwang, Yin-Tsung Chen, Jun-Yen Chiu, Jun-Jieh Natl Chung Hsing Univ Dept Elect Engn Taichung 40201 Taiwan

ISBN: (纸本)9780769532875

IP intergration in SoC nowadays contains two design aspects, i.e. hardware interface and software driver. The hardware interface supports necessary signal mapping, protocol translation and data buffering so that an IP can adapt to various system architectures. The software driver provides IP access controls from the software domain in the presence of operating system. The automation of both design processes in a coupling manner is addressed in this paper. We first outline the methodology of automatic interface synthesis and elaborate on the topics of signal mapping, protocol conversion and interface template architecture. We next present the framework of a baseline driver generator and detail the generation schemes of basic file operations and other functions and driver settings. Both tools are linked to form a HW/SW auto-coupling design suite, which features minimum user knowledge toward the hardware and OS details in usage. Some design examples on the interface synthesis tool and an JPEG codec HW/SW codesign example on the integrated design suite are provided to prove the effectiveness of the proposed system.

关键词： system-on-chip

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Work-in-Progress: A Simulation Framework for Domain-Specific system-on-Chips

Work-in-Progress: A Simulation Framework for Domain-Specific...

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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Arda, Samet E. Anish, N. K. Goksoy, A. Alper Mack, Joshua Kumbhare, Nirmal Sartor, Anderson L. Akoglu, Ali Marculescu, Radu Ogras, Umit Y. Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Univ Arizona Elect & Comp Engn Tucson AZ USA Carnegie Mellon Univ Elect & Comp Engn Pittsburgh PA 15213 USA

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A low-cost memory architecture with NAND XIP for mobile embedded systems

A low-cost memory architecture with NAND XIP for mobile embe...

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Park, C Seo, J Bae, S Kim, H Kim, S Kim, B Samsung Elect Co Ltd Software Ctr Seoul 135893 South Korea

ISBN: (纸本)1581137427

NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and high density. Even though NAND flash memory is gaining popularity as data storage, it can be also exploited as code memory for XIP (execute-in-place). In this paper, we present a new memory architecture which incorporates NAND flash memory into an existing memory hierarchy for code execution. The usefulness of the proposed approach is demonstrated with real embedded workloads on a real prototyping board.

关键词： memory architecture NAND XIP priority-based caching

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Work-in-Progress: EAST-DNN: Expediting Architectural SimulaTions Using Deep Neural Networks

Work-in-Progress: EAST-DNN: Expediting Architectural SimulaT...

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作者： Dutt, Arko Narasimman, Govind Jie, Lin Chandrasekhar, Vijay Ramaseshan Sabry, Mohamed M. NTU Singapore Singapore Singapore A STAR I2R Singapore Singapore Singapore

ISBN: (纸本)9781450369237

A rapid and accurate architectural simulator is a cornerstone for an efficient design-space exploration of computing systems. In this paper, we introduce EAST-DNN, a feed-forward deep neural network, to accelerate architectural simulations. EAST-DNN achieves > 106 x speedup with an average prediction error of 4.3% over the baseline simulator. It also achieves an average of 2x better accuracy with at least 2.3x speedup compared to state-of-the-art.

关键词： Deep Neural Network hardware Accelerators

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hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits 08

Hardware/software partitioning of floating point software ap...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Saldanha, Lance Lysecky, Roman Department of Electrical and Computer Engineering University of Arizona United States

ISBN: (纸本)9781605584706

While hardware/software partitioning has been shown to provide significant performance gains, most hardware/software partitioning approaches are limited to partitioning computational kernels utilizing integers or fixed point implementations. software developers often initially develop an application using built-in floating point representations and later convert the application to a fixed point representation - a potentially time consuming process. In this paper, we present a hardware/software partitioning approach for floating point applications that eliminates the need for developers to rewrite software applications for fixed point implementations. Instead, the proposed approach incorporates efficient, configurable floating point to fixed point and fixed point to floating point hardware converters at the boundary between the hardware coprocessors and memory. This effectively separates the system into a floating point domain consisting of the microprocessor and memory subsystem and a fixed point domain consisting of the partitioned hardware coprocessors, thereby providing an efficient and rapid method for implementing fixed point hardware coprocessors. Copyright 2008 ACM.

关键词： Coprocessor

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Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy for Blockchain Storage systems: Work-in-Progress

Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Liao, Jing Li, Zhengda Wang, Yi Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen Peoples R China Shenzhen Univ Natl Engn Lab Big Data Syst Comp Technol Shenzhen Peoples R China

ISBN: (纸本)9781728191980

Current LSM-Tree-based blockchain storage system will assign the data from multiple system users to the same disk drive. This will lead to the inefficient usage of physical spaces in disk and cause extra compaction operations for LSM-Tree. This paper presents Meta Chain, a user-aware cross-layer space allocation strategy for blockchain storage systems. As a cross-layer design, Meta-Chain redesigns the organization of LSM-Tree and utilizes the rich functionalities provided by open-channel SSD. Experimental results show that Meta-Chain can effectively reduce write amplification and extend the lifetime of SSD in comparison with representative schemes.

关键词： Blockchain Storage system LSM-Tree Flash Memory Space Allocation Address Translation

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Memory system design space exploration for low-power, real-time speech recognition

Memory system design space exploration for low-power, real-t...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Krishna, R Mahlke, S Austin, T Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA

ISBN: (纸本)1581139373

The recent proliferation of computing technology has generated new interest natural I/O interface technologies such as speech recognition. Unfortunately, the computational and memory demands of such applications currently prohibit their use on low-power portable devices in anything more than their simplest forms. Previous work has demonstrated that the thread level concurrency inherent in this application domain can be used to dramatically improve performance with minimal impact on overall system energy consumption, but that such benefits are severely constrained by memory system bandwidth. This work presents a design space exploration of potential memory system architectures. A range of low-power memory organizations are considered, from conventional caching to more advanced system-on-chip implementations. We find that, given architectures able to exploit concurrency in this domain, large L2 based cache hierarchies and high bandwidth memory systems employing data stream partitioning and on-chip embedded DRAM and ROM technologies can provide much of the performance of idealized memory systems without violating the power constraints of the low-power domain.

关键词： performance design

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Robust hardware-software Co-simulation framework for design and validation of Hybrid systems 20

Robust hardware-software Co-simulation framework for design ...

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20th ACM-IEEE international conference on Formal Methods and Models for system Design (MEMOCODE)

作者： Sood, Surinder Malik, Avinash Roop, Partha Univ Auckland Dept Elect & Comp eng Auckland New Zealand

ISBN: (数字)9798350331905

ISBN: (纸本)9798350331905

Model based design of embedded controllers is prevalent across different industries. The final step in model based design is synthesis of hardware (or software) controller and then testing the synthesized controller in closed-loop with the plant model - this is termed as co-simulation. Standard cosimulation approaches use asynchronous communication fabric. However, they are known to suffer from race conditions, jitter, etc, making real-time property validation difficult. Current approaches to co-simulation problems either require complex middle-ware or require synthesis of the controller and plant for synchronous execution. However, these approaches are unsuited for hybrid system control design and validation, as they require the plant model to execute at an arbitrarily small simulation step, while the synthesized controller executes at its own rate if any. The small simulation step slows down the simulation and such a setup does not guarantee level crossing detection. In this paper, we propose a novel Metric Interval Temporal Logic (MITL) based validation and hardware in Loop (HIL) co-simulation framework, which synchronizes and integrates the controller synthesized in hardware and the plant executing in software. A discrete controller handles a level crossing generated by the plant, which evolves on variable step size. The traces generated from the closed-loop operation of the overall system are used to validate MITL properties. Finally, the controller hardware and the plant model are adjoined via a communication architecture, whose sample time is dependent upon the robustness estimates of the MITL properties, which is necessary to guarantee validation correctness.

关键词： Co-simulation MITL Robustness validation Hybrid Automata (HA)

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Dynamic Property Mining for Embedded software 12

Dynamic Property Mining for Embedded Software

引用

10th ACM international conference on hardware/software-codesign and system synthesis

作者： Bonato, Marco Di Guglielmo, Giuseppe Fujita, Masahiro Fummi, Franco Pravadelli, Graziano Univ Verona Dept Comp Sci Str Grazie 15 I-37100 Verona Italy Univ Tokyo Japan Sci & Technol Agcy VLSI Design & Educ Ctr CREST Tokyo Japan

ISBN: (纸本)9781450314268

The importance of specification definition in the embedded-software design flow has been proven over the years. The entire design process relies on the specification quality, which inevitably depends on designer knowledge and skills. Automatic property mining is part of the efforts proposed to make this activity easier for the designers. Nonetheless, the existing approaches are limited to the detection of either arithmetic invariants of programs or temporal properties for Boolean designs, e.g., bit-level hardware descriptions. In this work, we present a dynamic mining approach able to infer linear temporal logic (LTL) properties for embedded software. The mined properties are in the form of temporal relationships between arithmetic expressions. The approach considers the execution traces only, thus it is completely independent from the code implementation. Experimental results demonstrate the effectiveness of the approach.

关键词： Temporal Property Dynamic Mining Embedded software

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Hw/Sw codesign of embedded systems 4th

引用

4th international conference on Reliable software Technologies (Ada-Europe'99)

作者： Fornaciari, W Sciuto, D Politecn Milan Dipartimento Elettron & Informaz I-20133 Milan Italy

ISBN: (纸本)3540660933

The architecture of systems tailored for a specific application frequently requires cooperation among hardware and software components. The design of these systems is typically a compromise among a number of factors: cost, performance, size, development time, power consumption, etc. To cope with increasing possibilities offered by nowadays integration technology and steady demanding of shorter time-to-market, a comprehensive strategy aiming at gathering all the involved aspects of the design is becoming mandatory This new discipline, called codesign, considers in a concurrent manner all the activities involved in the design of a mixed hw/sw dedicated system: capturing of design specification and requirements, mapping of the design onto hardware and software domains, system synthesis and design verification. The paper introduces the key factors involved in the design of an embedded system, together with a description on how codesign is overcoming such problems, opening the way to a new generation of CAD frameworks supporting system-level design.

关键词： Embedded systems

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