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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"
853 条 记 录,以下是161-170 订阅
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Will My Program Break on This Faulty Processor?: Formal Analysis of hardware Fault Activations in Concurrent Embedded software
Will My Program Break on This Faulty Processor?: Formal Anal...
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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)
作者: Bajczi, Levente Voros, Andras Molnar, Vince Budapest Univ Technol & Econ Fault Tolerant Syst Res Grp Dept Measurement & Informat Syst POB 91 H-1521 Budapest Hungary MTA BME Lendulet Cyber Phys Syst Res Grp Budapest Hungary
Formal verification is approaching a point where it will be reliably applicable to embedded software. Even though formal verification can efficiently analyze multi-threaded applications, multi-core processors are ofte... 详细信息
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Compositional Design of Multi-Robot systems Control software on ROS
Compositional Design of Multi-Robot Systems Control Software...
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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)
作者: Spellini, Stefano Lora, Michele Fummi, Franco Chattopadhyay, Sudipta Univ Verona Dept Comp Sci Str Grazie 15 I-37134 Verona Italy Singapore Univ Technol & Design ISTD 8 Somapah Rd Singapore 487372 Singapore
This paper presents a methodology that relies on Assume-Guarantee Contracts to decompose the problem of synthesizing control software for a multi-robot system. Initially, each contract describes either a component (e.... 详细信息
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Parametric Scheduler Characterization
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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年 第5期18卷 1-25页
作者: Van Pinxten, Joost Geilen, Marc Basten, Twan Oce Technol BV POB 101 NL-5900 MA Venlo Netherlands Eindhoven Univ Technol Groene Loper 19Flux 4-132 NL-5612 AZ Eindhoven Netherlands TNO ESI Eindhoven Netherlands
Schedulers assign starting times to events in a system such that a set of constraints is met and system productivity is maximized. We characterize the scheduler behaviour for the case where decisions are made by compa... 详细信息
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ReSQM: Accelerating Database Operations Using ReRAM-Based Content Addressable Memory
ReSQM: Accelerating Database Operations Using ReRAM-Based Co...
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作者: Li, Huize Jin, Hai Zheng, Long Liao, Xiaofei National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China
The huge amount of data enforces great pressure on the processing efficiency of database systems. By leveraging the in-situ computing ability of emerging nonvolatile memory, processing-in-memory (PIM) technology shows... 详细信息
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Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices
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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2021年 第5期20卷 71-71页
作者: Zhang, Xinyi Wu, Yawen Zhou, Peipei Tang, Xulong Hu, Jingtong Univ Pittsburgh Swanson Sch Engn Elect & Comp Engn Pittsburgh PA 15260 USA Univ Pittsburgh Sch Comp & Informat Comp Sci Pittsburgh PA 15260 USA
Multi-head self-attention (attention mechanism) has been employed in a variety of fields such as machine translation, language modeling, and image processing due to its superiority in feature extraction and sequential... 详细信息
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international conference on Compilers, Architecture, and synthesis for Embedded systems (CODES +ISSS) 2019 - Table of Contents
International Conference on Compilers, Architecture, and Syn...
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international conference on hardware/software codesign and system synthesis (CODES)
Presents the table of contents/splash page of the proceedings record.
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MARS: mm Wave-based Assistive Rehabilitation system for Smart Healthcare
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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2021年 第5期20卷 72-72页
作者: An, Sizhe Ogras, Umit Y. Univ Wisconsin Dept Elect & Comp Engn Madison WI 53706 USA
Rehabilitation is a crucial process for patients suffering from motor disorders. The current practice is performing rehabilitation exercises under clinical expert supervision. New approaches are needed to allow patien... 详细信息
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Synterface: Efficient Chip-to-World Interfacing for Flow-Based Microfluidic Biochips Using Pin-Count Minimization
Synterface: Efficient Chip-to-World Interfacing for Flow-Bas...
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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)
作者: Sridhar, Aditya Ibrahim, Mohamed Chakrabarty, Krishnendu Duke Univ Dept Elect & Comp Engn 130 Hudson Hall Durham NC 27708 USA
Flow-based microfluidic biochips can be used to perform bioassays by manipulating a large number of on-chip valves. These biochips are increasingly used today for biomolecular recognition, single-cell screening, and p... 详细信息
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Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS
Cache Locking Content Selection Algorithms for ARINC-653 Com...
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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)
作者: Dugo, Alexy Torres Aurora Lefoul, Jean-Baptiste De Magalhaes, Felipe Gohring Assal, Dahman Nicolescu, Gabriela Ecole Polytech Montreal 2900 Boul Edouard Montpetit Montreal PQ Canada Mannarino Syst & Software Inc Montreal PQ Canada
Avionic software is the subject of stringent real time, determinism and safety constraints. software designers face several challenges, one of them being the interferences that appear in common situations, such as res... 详细信息
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Work-in-Progress: Offloading Cache Configuration Prediction to an FPGA for hardware Speedup and Overhead Reduction
Work-in-Progress: Offloading Cache Configuration Prediction ...
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international conference on hardware/software codesign and system synthesis (CODES)
作者: Ruben Vazquez Ann Gordon-Ross Greg Stitt University of Florida Gainesville United States
In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of th...
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