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Towards Scalable Symbolic Routing for Multi-Objective Networked Embedded system Design and Optimization 14

Towards Scalable Symbolic Routing for Multi-Objective Networ...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Graf, Sebastian Reimann, Felix Glass, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Erlangen Germany

ISBN: (纸本)9781450330510

Symbolic encoding for resource allocation, task binding, and message routing during multi-objective design space exploration (DSE) has gained significant attention in recent years. To determine the message routing, existing symbolic approaches typically rely on an explicit encoding of routing hops which results in a huge number of required variables and/or constraints. As a result, these approaches fail in case of large network diameters and/or a huge number of messages or resources and even for smaller problems, the convergence of the involved optimization process suffers. To tackle this shortcomings, this work proposes three novel symbolic routing encoding strategies that all avoid to encode hops explicitly, but are based on an encoding of individual links or complete sender-receiver paths, but still cover the same design space. The result is a more compact problem representation with less constraints and, in particular, less variables;the latter eliminates ineffective degrees of freedom from the search space and significantly enhances the optimization quality of a multi-objective optimization with even non-linear objectives. In an extensive test-suite, three major classes of wired networked embedded systems are considered: (a) hierarchical stars as in MPSoCs or automotive, (b) redundant backbone buses as common in rail systems or avionics, and (c) mesh-based architectures that often occur in NoC-based MPSoCs. For all three classes, the proposed approaches significantly outperform existing techniques in both scalability and optimization quality and, thus, considerably enlarge the field of application of a multi-objective DSE for the networked embedded system design.

关键词： Embedded systems Encoding Optimization Receivers Resource management Routing Scalability Network routing Scalability Embedded systems embedded system design management of resources Receivers coding

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A study of transistor degradation in cyber-physical system control devices: Work-in-progress 21

A study of transistor degradation in cyber-physical system c...

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2021 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2021

作者： Millican, Spencer Griffith, SueAnne Auburn University Department of Electrical and Computer Engineering Samuel Ginn College of Engineering AuburnAL United States

ISBN: (纸本)9781450390767

This work presents a plan for investigating transistor aging and degradation in cyber physical systems under attack. The authors discuss the importance of such concerns, particularly with regard to negative bias temperature instability, and an approach to demonstrate the adverse effects of a cyber-attack resulting in premature aging of transistors within a system's digital controllers. © 2021 ACM.

关键词： Cyber Physical system

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How to Enable software Isolation and Boost system Performance with Sub-block Erase over 3D Flash Memory 16

How to Enable Software Isolation and Boost System Performanc...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Chang, Hsin-Yu Ho, Chien-Chung Chang, Yuan-Hao Chang, Yu-Ming Kuo, Tei-Wei Macronix Int Co Ltd Hsinchu Taiwan Acad Sinica Inst Informat Sci Taipei Taiwan Acad Sinica Res Ctr Informat Technol Innovat Taipei Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan

ISBN: (纸本)9781450344838

The write amplification problem deteriorates as the block size of modern flash-memory chips keeps increasing. Without the careful garbage collection, significant live-page copying might even worsen the reliability problem, that is already severe to 3D flash memory. In this work, we propose a sub-block erase design to not only alleviate the write amplification problem by reducing live-page copying but also improve the system reliability with a software isolation strategy. In particular, sub-blocks are carefully allocated to satisfy write requests so as to reduce disturbance by using free or invalid sub-blocks as isolation layers among sub-blocks, without additional hardware cost and capacity loss. A series of experiments were conducted to evaluate the capability of the proposed design. The results show that the proposed design is very effective in improving the system performance by reducing garbage collection overheads and in improving the device reliability/lifetime.

关键词： Flash memory

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Computer Security by hardware-Intrinsic Authentication

Computer Security by Hardware-Intrinsic Authentication

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hoffman, Caio Cortes, Mario Aranha, Diego F. Araujo, Guido Univ Estadual Campinas Inst Comp Campinas SP Brazil

ISBN: (纸本)9781467383219

The widespread embedding of electronic devices into the daily-life objects, and their integration in the so called Internet of the Things ( IoT), has raised a number of challenges for the design of systems-on-Chip ( SoCs) devices. Tiny manufacturing costs, stringent security, and ultra-low power operation constraints have considerably raised SoC design requirements. More than incremental approaches which try to re-use current cryptographic mechanisms, the new generation of IoT devices will require novel solutions which deeply integrate their hardware-intrinsic features to program execution. This paper proposes a low-cost PUF-based authentication architecture aiming to secure code execution in IoT SoCs. The solution is deeply embedded into the processor micro-architecture, so as to minimize re-design costs and performance penalties. This new architecture model not only deals with the most common threats against code and data authenticity and integrity, but also provides an approach to extract from processor's caches a stable and unpredictable key that is used in the code and data authentication process.

关键词： Internet of Things authorisation cache storage computer architecture cryptography data integrity system-on-chip Internet of the things IoT SoC computer security cryptographic mechanisms daily-life objects data authentication process data authenticity electronic devices hardware-intrinsic authentication hardware-intrinsic features low-cost PUF-based authentication architecture processor caches processor microarchitecture systems-on-chip device design Authentication Computer architecture Cryptography Performance evaluation Random access memory software Computer Architecture Data Quality cryptography Computer Security system-on-chip Electron devices random access machine cache storage Internet of things Authentication Authorization Performance Evaluation computer software

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Facilitating reuse in hardware models with enhanced type inference

Facilitating reuse in hardware models with enhanced type inf...

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Second IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004

作者： Vachharajani, Manish Vachharajani, Neil Malik, Sharad August, David I. Depts. of Comp. Sci. and Elec. Eng. Princeton University Princeton NJ 08544 United States

ISBN: (纸本)1581139373

High-level hardware modeling is an essential, yet time-consuming, part of system design. However, effective component-based reuse in hardware modeling languages can reduce model construction time and enable the exploration of more design alternatives, leading to better designs. While component overloading and parametric polymorphism are critical for effective component-base reuse, no existing modeling language supports both. The lack of these features creates overhead for designers that discourages reuse, negating any benefits of reuse. This paper presents a type system which supports both component overloading and parametric polymorphism. It proves that performing type inference for any such system is NP-complete and presents a heuristic that works efficiently in practice. The result is a type system and type inference algorithm that can encourage reuse, reduce design specification time, and lead to better designs.

关键词： Computer software reusability

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An Accurate and Flexible Early Memory system Power Evaluation Approach Using a Microcomponent Method 16

An Accurate and Flexible Early Memory System Power Evaluatio...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Chen, Chi-Kang Wu, Hsin-I Hsiao, Chi-Ting Tsay, Ren-Song Natl Tsing Hua Univ Dept Comp Sci Hsinchu Taiwan Ind Technol Res Inst Hsinchu Taiwan

ISBN: (纸本)9781450344838

As energy efficiency has become a primary concern, system designers have greater need for a flexible and highly accurate power estimation method for evaluating different architecture options. Since memory is an increasingly dominant power consumer, we reexamine existing memory power models and propose a highly efficient microcomponent-based approach with data-aware refinement for accurate system-level power estimations. The key contribution of our approach is that the proposed microcomponent method allows designers to use flexible architecture compositions. Our approach identifies the common microcomponents used by internal memory commands and accurately pre-calibrates the power consumption pattern of each microcomponent. We decompose target design architectures into these microcomponents to easily derive accurate power estimates. To achieve very high accuracy, we consider the data variation effect by leveraging the fact that memory circuit is mainly doing data passing and hence a simple interpolation technique can further boost accuracy. Our experiments show that the proposed approach produces accurate results of less than 2% error rate in average for system power analysis.

关键词： Energy efficiency

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system level synthesis of hardware for DSP applications using pre-characterized function implementations

System level synthesis of hardware for DSP applications usin...

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11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Li, Shuo Farahini, Nasim Hemani, Ahmed Rosvall, Kathrin Sander, Ingo ES/ICT/KTH Forum 120 SE-164 40 Kista Sweden

ISBN: (纸本)9781479914173

SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized function implementations (FTMPs). It explores the design space in three dimensions, number of FTMPs, type of FTMPs and pipeline parallelism between the producing and consuming FTMPs. We introduce timing and interface model of FTMPs to enable reuse and automatic generation of Global Interconnect and Control (GLIC) to glue the FTMPs together into a working system. SYLVA has been evaluated by applying it to five realistic DSP applications and results analyzed for design space exploration, efficacy in generating GLIC by comparing to manually generated GLIC and accuracy of design space exploration by comparing the area and energy costs considered during the design space exploration based on pre-characterized FIMPs and the final results. © 2013 IEEE.

关键词： Data transfer

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Increasing hardware efficiency with multifunction loop accelerators

Increasing hardware efficiency with multifunction loop accel...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Fan, Kevin Kudlur, Manjunath Park, Hyunchul Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595933700

To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally designed in a single-function manner, wherein each loop nest is implemented as a dedicated hardware block. This paper focuses on hardware sharing across loop nests by creating multifunction loop accelerators, or accelerators capable of executing multiple algorithms. A compiler-based system for automatically synthesizing multifunction loop accelerator architectures from C code is presented. We compare the effectiveness of three architecture synthesis approaches with varying levels of complexity: sum of individual accelerators, union of individual accelerators, and joint accelerator synthesis. Experiments show that multifunction accelerators achieve substantial hardware savings over combinations of single-function designs. In addition, the union approach to multifunction synthesis is shown to be effective at creating low-cost hardware by exploiting hardware sharing, while remaining computationally tractable. © Copyright 2006 ACM.

关键词： Computer hardware

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SEAS: A system for early analysis of SoCs

SEAS: A system for early analysis of SoCs

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Bergamaschi, RA Shin, YS Dhanwada, N Bhattacharya, S Dougherty, WE Nair, I Darringer, J Paliwal, S IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)1581137427

systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are pre-designed and pre-verified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early design decisions regarding performance, area, timing and power;and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.

关键词： design analysis design space exploration performance power floorplanning

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Conquering MPSoC Complexity with Principles of a Self-Aware Information Processing Factory 16

Conquering MPSoC Complexity with Principles of a Self-Aware ...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Dutt, Nikil Kurdahi, Fadi J. Ernst, Rolf Herkersdorf, Andreas Univ Calif Irvine Ctr Embedded & Cyber Phys Syst Irvine CA 92697 USA Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Tech Univ Munich D-80290 Munich Germany

ISBN: (纸本)9781450344838

We introduce the idea of an Information Processing Factory as a step towards autonomous many-core platforms in Cyber-Physical systems (CPS) and the Internet of Things (IoT). It represents a paradigm shift in platform design moving long term, with robust and independent platform operation in the focus of platform-centric design rather than existing semiconductor device or software technology, as mostly seen today. Such a refocus is not only needed to prepare for the time when technology scaling comes to an end, but is a necessity to manage complexity when networked IT systems not only by far outnumber humans but when their complexity by far exceeds that of human societies. While such applications complexity growth is visible to large parts of the society, and is publicly discussed, it is important to note that the complexity growth equally affects the platforms (computers, communication, storage, etc.) which enable such growing applications. This challenge is partly addressed by the new areas of Cyber-Physical systems and the Internet-of-Things, but the changing challenges to the operation of complex microelectronic systems is mostly left to computer and software architects, and to semiconductor technology. This perspective paper motivates the necessity for a paradigm shift in IT system design and its application to autonomous systems as a main application.

关键词： Self-awareness system-on-Chip cyber-physical systems

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