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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"
853 条 记 录,以下是171-180 订阅
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Towards Scalable Symbolic Routing for Multi-Objective Networked Embedded system Design and Optimization  14
Towards Scalable Symbolic Routing for Multi-Objective Networ...
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international conference on hardware / software codesign and system synthesis (CODES+ISSS)
作者: Graf, Sebastian Reimann, Felix Glass, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Erlangen Germany
Symbolic encoding for resource allocation, task binding, and message routing during multi-objective design space exploration (DSE) has gained significant attention in recent years. To determine the message routing, ex... 详细信息
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A study of transistor degradation in cyber-physical system control devices: Work-in-progress  21
A study of transistor degradation in cyber-physical system c...
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2021 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2021
作者: Millican, Spencer Griffith, SueAnne Auburn University Department of Electrical and Computer Engineering Samuel Ginn College of Engineering AuburnAL United States
This work presents a plan for investigating transistor aging and degradation in cyber physical systems under attack. The authors discuss the importance of such concerns, particularly with regard to negative bias tempe... 详细信息
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How to Enable software Isolation and Boost system Performance with Sub-block Erase over 3D Flash Memory  16
How to Enable Software Isolation and Boost System Performanc...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Chang, Hsin-Yu Ho, Chien-Chung Chang, Yuan-Hao Chang, Yu-Ming Kuo, Tei-Wei Macronix Int Co Ltd Hsinchu Taiwan Acad Sinica Inst Informat Sci Taipei Taiwan Acad Sinica Res Ctr Informat Technol Innovat Taipei Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan
The write amplification problem deteriorates as the block size of modern flash-memory chips keeps increasing. Without the careful garbage collection, significant live-page copying might even worsen the reliability pro... 详细信息
来源: 评论
Computer Security by hardware-Intrinsic Authentication
Computer Security by Hardware-Intrinsic Authentication
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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Hoffman, Caio Cortes, Mario Aranha, Diego F. Araujo, Guido Univ Estadual Campinas Inst Comp Campinas SP Brazil
The widespread embedding of electronic devices into the daily-life objects, and their integration in the so called Internet of the Things ( IoT), has raised a number of challenges for the design of systems-on-Chip ( S... 详细信息
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Facilitating reuse in hardware models with enhanced type inference
Facilitating reuse in hardware models with enhanced type inf...
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Second IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004
作者: Vachharajani, Manish Vachharajani, Neil Malik, Sharad August, David I. Depts. of Comp. Sci. and Elec. Eng. Princeton University Princeton NJ 08544 United States
High-level hardware modeling is an essential, yet time-consuming, part of system design. However, effective component-based reuse in hardware modeling languages can reduce model construction time and enable the explor... 详细信息
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An Accurate and Flexible Early Memory system Power Evaluation Approach Using a Microcomponent Method  16
An Accurate and Flexible Early Memory System Power Evaluatio...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Chen, Chi-Kang Wu, Hsin-I Hsiao, Chi-Ting Tsay, Ren-Song Natl Tsing Hua Univ Dept Comp Sci Hsinchu Taiwan Ind Technol Res Inst Hsinchu Taiwan
As energy efficiency has become a primary concern, system designers have greater need for a flexible and highly accurate power estimation method for evaluating different architecture options. Since memory is an increa... 详细信息
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system level synthesis of hardware for DSP applications using pre-characterized function implementations
System level synthesis of hardware for DSP applications usin...
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11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013
作者: Li, Shuo Farahini, Nasim Hemani, Ahmed Rosvall, Kathrin Sander, Ingo ES/ICT/KTH Forum 120 SE-164 40 Kista Sweden
SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized funct... 详细信息
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Increasing hardware efficiency with multifunction loop accelerators
Increasing hardware efficiency with multifunction loop accel...
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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis
作者: Fan, Kevin Kudlur, Manjunath Park, Hyunchul Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally design... 详细信息
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SEAS: A system for early analysis of SoCs
SEAS: A system for early analysis of SoCs
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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis
作者: Bergamaschi, RA Shin, YS Dhanwada, N Bhattacharya, S Dougherty, WE Nair, I Darringer, J Paliwal, S IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA
systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are pre-designed and pre-verified, when they are assembled in an SoC there is no ... 详细信息
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Conquering MPSoC Complexity with Principles of a Self-Aware Information Processing Factory  16
Conquering MPSoC Complexity with Principles of a Self-Aware ...
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international conference on hardware/software codesign and system synthesis (CODES+ISSS)
作者: Dutt, Nikil Kurdahi, Fadi J. Ernst, Rolf Herkersdorf, Andreas Univ Calif Irvine Ctr Embedded & Cyber Phys Syst Irvine CA 92697 USA Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Tech Univ Munich D-80290 Munich Germany
We introduce the idea of an Information Processing Factory as a step towards autonomous many-core platforms in Cyber-Physical systems (CPS) and the Internet of Things (IoT). It represents a paradigm shift in platform ... 详细信息
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