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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Van Pinxten, Joost Geilen, Marc Basten, Twan Oce Technol BV POB 101 NL-5900 MA Venlo Netherlands Eindhoven Univ Technol Groene Loper 19Flux 4-132 NL-5612 AZ Eindhoven Netherlands TNO ESI Eindhoven Netherlands

Schedulers assign starting times to events in a system such that a set of constraints is met and system productivity is maximized. We characterize the scheduler behaviour for the case where decisions are made by comparing affine expressions of design parameters such as task workload, processing speed, robot travelling speed, or a controller's rise and settling time. Deterministic schedulers can be extended with symbolic execution, to keep track of the affine conditions on the parameters for which the scheduling decisions are made. We introduce a divide-and-conquer algorithm that uses this information to determine parameter regions for which the same sequence of decisions is taken given a particular scenario. The results provide designers insight in the impact of parameter changes on the performance of their system. The exploration can also be executed with the KLEE symbolic execution engine of the LLVM tool chain to extract the same results. We show that the divide-and-conquer approach provides the results much faster than the generic symbolic execution engine of KLEE. The results allow visualization of the sensitivity to all parameter combinations. The results of our approach therefore provide more insight in the sensitivity to parameters.

关键词： Real time scheduling system design re-entrant flexible manufacturing system

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Polar: Function Code Aware Fuzz Testing of ICS Protocol

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 1-22页

作者： Luo, Zhengxiong Zuo, Feilong Jiang, Yu Gao, Jian Jiao, Xun Sun, Jiaguang Tsinghua Univ Sch Software BNRist KLISS Beijing Peoples R China Villanova Univ Dept Comp Sci & Engn Villanova PA 19085 USA

Industrial Control system (ICS) protocols are widely used to build communications among system components. Compared with common internet protocols, ICS protocols have more control over remote devices by carrying a specific field called "function code", which assigns what the receive end should do. Therefore, it is of vital importance to ensure their correctness. However, traditional vulnerability detection techniques such as fuzz testing are challenged by the increasing complexity of these diverse ICS protocols. In this paper, we present a function code aware fuzzing framework - Polar, which automatically extracts semantic information from the ICS protocol and utilizes this information to accelerate security vulnerability detection. Based on static analysis and dynamic taint analysis, Polar initiates the values of the function code field and identifies some vulnerable operations. Then, novel semantic aware mutation and selection strategies are designed to optimize the fuzzing procedure. For evaluation, we implement Polar on top of two popular fuzzers - AFL and AFLFast, and conduct experiments on several widely used ICS protocols such as Modbus, IEC104, and IEC 61850. Results show that, compared with AFL and AFLFast, Polar achieves the same code coverage and bug detection numbers at the speed of 1.5X-12X. It also gains increase with 0%-91% more paths within 24 hours. Furthermore, Polar has exposed 10 previously unknown vulnerabilities in those protocols, 6 of which have been assigned unique CVE identifiers in the US National Vulnerability Database.

关键词： Fuzz testing industrial control system protocol function code vulnerability detection

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An Ultra-Low Energy Human Activity Recognition Accelerator for Wearable Health Applications

An Ultra-Low Energy Human Activity Recognition Accelerator f...

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作者： Bhat, Ganapati Tuncel, Yigit An, Sizhe Lee, Hyung Gyu Ogras, Umit Y. Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Daegu Univ Sch Comp & Commun Engn Daegu 38453 South Korea

Human activity recognition (HAR) has recently received significant attention due to its wide range of applications in health and activity monitoring. The nature of these applications requires mobile or wearable devices with limited battery capacity. User surveys show that charging requirement is one of the leading reasons for abandoning these devices. Hence, practical solutions must offer ultra-low power capabilities that enable operation on harvested energy. To address this need, we present the first fully integrated custom hardware accelerator (HAR engine) that consumes 22.4 mu J per operation using a commercial 65 nm technology. We present a complete solution that integrates all steps of HAR, i.e., reading the raw sensor data, generating features, and activity classification using a deep neural network (DNN). It achieves 95% accuracy in recognizing 8 common human activities while providing three orders of magnitude higher energy efficiency compared to existing solutions.

关键词： Human activity recognition wearable electronics flexible hybrid electronics hardware accelerator low-power design health monitoring

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Work-in-Progress: EAST-DNN: Expediting Architectural SimulaTions Using Deep Neural Networks

Work-in-Progress: EAST-DNN: Expediting Architectural SimulaT...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Arko Dutt Govind Narasimman Lin Jie Vijay Ramaseshan Chandrasekhar Mohamed M. Sabry NTU Singapore A*STAR I2R Singapore

A rapid and accurate architectural simulator is a cornerstone for an emcient design-space exploration of computing systems. In this paper, we introduce EAST-DNN, a feed-forward deep neural network, to accelerate architectural simulations. EAST-DNN achieves > 10 6 × speedup with an average prediction error of 4.3% over the baseline simulator. It also achieves an average of 2× better accuracy with at least 2.3× speedup compared to state-of-the-art.

关键词： Radio frequency Neural networks Acceleration hardware Boosting Training Computational modeling

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Deriving Equations from Sensor Data Using Dimensional Function synthesis

Deriving Equations from Sensor Data Using Dimensional Functi...

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作者： Wang, Youchao Willis, Sam Tsoutsouras, Vasileios Stanley-Marbell, Phillip Univ Cambridge 9 JJ Thomson Ave Cambridge CB3 0FA England

We present a new method for deriving functions that model the relationship between multiple signals in a physical system. The method, which we call dimensional function synthesis, applies to data streams where the dimensions of the signals are known. The method comprises two phases: a compile-time synthesis phase and a subsequent calibration using sensor data. We implement dimensional function synthesis and use the implementation to demonstrate efficiently summarizing multi-modal sensor data for two physical systems using 90 laboratory experiments and 10 000 synthetic idealized measurements. We evaluate the performance of the compile-time phase of dimensional function synthesis as well as the calibration phase overhead, inference latency, and accuracy of the models our method generates. The results show that our technique can generate models in less than 300 ms on average across all the physical systems we evaluated. When calibrated with sensor data, our models outperform traditional regression and neural network models in inference accuracy in all the cases we evaluated. In addition, our models perform better in training latency (over 8660x improvement) and required arithmetic operations in inference (over 34x improvement). These significant gains are largely the result of exploiting information on the physics of signals that has hitherto been ignored.

关键词： Machine learning dimensional analysis sensor data fusion

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Work-in-Progress: Drama: A High Efficient Neural Network Accelerator on FPGA using Dynamic Reconfiguration

Work-in-Progress: Drama: A High Efficient Neural Network Acc...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Yang Yang Chao Wang Xuehai Zhou University of Science and Technology of China Suzhou China

In this paper, we propose a high efficient neural network accelerator on FPGA by using dynamic reconfiguration, named Drama. Firstly, we design a high-efficient hardware architecture and provide a hardware template that can generate optimal configuration for each layer. Then, to explore the key features of the neural network models, we employ a layer-clustering algorithm to classify different layers. After that, we transform CNN models into task sequences. To accomplish the execution of the sequence, the FPGA-based hardware is able to switch the accelerator with dynamic reconfiguration and offload the related tasks to the accelerator at runtime. Preliminary results on the FPGA platform demonstrate that Drama is able to improve the performance significantly due to the dynamic reconfiguration techniques.

关键词： Field programmable gate arrays hardware Neural networks Task analysis Parallel processing Bandwidth Runtime

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Polar: Function Code Aware Fuzz Testing of ICS Protocol

Polar: Function Code Aware Fuzz Testing of ICS Protocol

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关键词： Fuzz testing industrial control system protocol function code vulnerability detection

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Work-in-Progress: A Simulation Framework for Domain-Specific system-on-Chips

Work-in-Progress: A Simulation Framework for Domain-Specific...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Samet E. Arda NK Anish A. Alper Goksoy Joshua Mack Nirmal Kumbhare Anderson L. Sartor Ali Akoglu Radu Marculescu Umit Y. Ogras School of Electrical Computer and Energy Engineering Arizona State University Tempe AZ USA Electrical and Computer Engineering The University of Arizona Tucson AZ USA Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Homogeneous general purpose processors provide flexibility to implement a variety of applications and facilitate programmability. In contrast, heterogeneous system-on-chips (SoCs) that combine general purpose and specialized processors offer great potential to achieve higher efficiency while maintaining programming flexibility. In particular, domain-specific SoCs (DSSoC), a class of heterogeneous architectures, tailor the architecture and processing elements (PE) to a specific domain. Hence, they can provide superior energy-efficiency compared to general purpose processors by exploiting the characteristics of target applications.

关键词： Task analysis Schedules Computer architecture Heuristic algorithms Dynamic scheduling hardware

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Work-in-Progress: A concept of a hardware design environment with the functional language Elixir

Work-in-Progress: A concept of a hardware design environment...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hideki Takase Kentaro Matsui Yoshihiro Ueno Masakazu Mori Yuki Hisae Susumu Yamazaki JST PRESTO Japan Kyoto University Sakyo-ku Kyoto Japan Delight Systems Co. Ltd. Chuo-ku Fukuoka Japan Karabiner Technology Inc. Chuo-ku Fukuoka Japan The University of Kitakyushu Wakamatsu-ku Kitakushu Japan

The functional language Elixir is designed to be effective for the application. One of the most considerable feature of Elixir is that it is easy to realize the parallel processing with the standard library, such as Flow. In this paper, we study a design environment for hardware circuits using Elixir as a design language. We propose a synthesize flow for data flow hardware on the FPGA from the native Elixir code. Our method synthesizes functional equivalence circuits from the description of Enum and Flow in Elixir, which are libraries for direct manipulation and parallel processing of data collection in Elixir. Data flow is implemented base on the pipeline operator which connects the processing relation of the function by the data processing order. To realize a hardware design environment by Elixir, this paper shares current status of our implementation.

关键词： hardware Field programmable gate arrays hardware design languages Distributed databases IP networks Parallel processing Pipelines

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High-Level synthesis of Approximate Designs under Real-Time Constraints

High-Level Synthesis of Approximate Designs under Real-Time ...

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作者： Leipnitz, Marcos T. Nazar, Gabriel L. Univ Fed Rio Grande do Sul Informat Inst Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

The adoption of High-Level synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

关键词： High-level synthesis approximate computing worst-case execution time design space exploration

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