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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 853 条记录，以下是181-190 订阅

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Work-in-Progress: Runtime Requirements Monitoring for State-based hardware

Work-in-Progress: Runtime Requirements Monitoring for State-...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Seo, Minjun Lysecky, Roman Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

ISBN: (纸本)9781538655627

This paper presents a requirements-driven methodology enabling efficient runtime monitoring of hardware in embedded systems. We present a novel method for extracting hardware verification requirements from state-based hardware models to construct a hierarchical runtime monitoring graph (HRMG) that can be efficiently used at runtime to verify correctness.

关键词： Runtime requirements verification hardware verification formal verification models non-intrusive monitoring

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2015 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2015

2015 International Conference on Hardware/Software Codesign ...

引用

international conference on hardware/software codesign and system synthesis, CODES+ISSS 2015

ISBN: (纸本)9781467383219

The proceedings contain 24 papers. The topics discussed include: how to improve the space utilization of Dedup-based PCM storage devices?;a tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones;lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs;improved hard real-time scheduling of CSDF-modeled streaming applications;hardware synthesis from a recursive functional language;power-awareness and smart-resource management in embedded computing systems;an online wear state monitoring methodology for off-the-shelf embedded processors;big/little deep neural network for ultra low power inference;an approximate compressor for wearable biomedical healthcare monitoring systems;and fast parallel application and multiprocessor design space exploration from sequential code.

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Statistical Verification of Hyperproperties for Cyber-Physical systems

Statistical Verification of Hyperproperties for Cyber-Physic...

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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Wang, Yu Zarei, Mojtaba Bonakdarpour, Borzoo Pajic, Miroslav Duke Univ 100 Sci DrHudson Hall Rm 220 Durham NC 27708 USA Iowa State Univ 207 Atanasoff Hall Ames IA 50011 USA

Many important properties of cyber-physical systems (CPS) are defined upon the relationship between multiple executions simultaneously in continuous time. Examples include probabilistic fairness and sensitivity to modeling errors (i.e., parameters changes) for real-valued signals. These requirements can only be specified by hyperproperties. In this article, we focus on verifying probabilistic hyperproperties for CPS. To cover a wide range of modeling formalisms, we first propose a general model of probabilistic uncertain systems (PUSs) that unify commonly studied CPS models such as continuous-time Markov chains (CTMCs) and probabilistically parametrized Hybrid I/O Automata (P(2)HIOA). To formally specify hyperproperties, we propose a new temporal logic, hyper probabilistic signal temporal logic (HyperPSTL) that serves as a hyper and probabilistic version of the conventional signal temporal logic (STL). Considering the complexity of real-world systems that can be captured as PUSs, we adopt a statistical model checking (SMC) approach for their verification. We develop a new SMC technique based on the direct computation of significance levels of statistical assertions for HyperPSTL specifications, which requires no a priori knowledge on the indifference margin. Then, we introduce SMC algorithms for HyperPSTL specifications on the joint probabilistic distribution of multiple paths, as well as specifications with nested probabilistic operators quantifying different paths, which cannot be handled by existing SMC algorithms. Finally, we show the effectiveness of our SMC algorithms on CPS benchmarks with varying levels of complexity, including the Toyota Powertrain Control system.

关键词： Cyber-physical systems hyperproperties statistical model checking embedded control software

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Work-in-Progress: hardware Implementation of a Multi-Mode-Aware Mixed-Criticality Scheduler

Work-in-Progress: Hardware Implementation of a Multi-Mode-Aw...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hounsinou, Sena Vasu, Aishwarya Ramaprasad, Harini Southern Illinois Univ Carbondale IL 62901 USA Univ N Carolina Charlotte NC USA

ISBN: (纸本)9781538655627

To minimize size, weight, power, and cost, the industry aims at consolidating different criticality applications on the same hardware platform. In such a mixed-criticality environment, it is challenging to contain the overhead due to potential mode changes under overload conditions. Traditional scheduler implementation at the software level introduces additional overheads due to timer interrupt processing and context switching. To minimize overall software overhead and to improve timing predictability, in this paper, we propose an implementation of the mixed-criticality scheduler in the hardware that is capable of detecting task-overruns and making mode transitions seamlessly.

关键词： Task analysis hardware Real-time systems Monitoring Registers software Processor scheduling

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SWARAM: Portable Energy and Cost Efficient Embedded system for Genomic Processing

SWARAM: Portable Energy and Cost Efficient Embedded System f...

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作者： Mohanty, Ram Prasad Gamaarachchi, Hasindu Lambert, Andrew Parameswaran, Sri Univ New South Wales Canberra ACT 2612 Australia Univ New South Wales Sydney NSW 2052 Australia

Treatment of patients using high-quality precision medicine requires a thorough understanding of the genetic composition of a patient. Ideally, the identification of unique variations in an individual's genome is needed for specifying the necessary treatment. Variant calling workflow is a pipeline of tools, integrating state of the art software systems aimed at alignment, sorting and variant calling for the whole genome sequencing (WGS) data. This pipeline is utilized for identifying unique variations in an individual's genome (compared to a reference genome). Currently, such a workflow is implemented on high-performance computers (with additional GPUs or FPGAs) or in cloud computers. Such systems are large, have a high cost, and rely on the internet for genome data transfer which makes the system unusable in remote locations unequipped with internet connectivity. It further raises privacy concerns due to processing being carried out in a different facility. To overcome such limitations, in this paper, for the first time, we present a cost-efficient, offline, scalable, portable, and energy-efficient computing system named SWARAM for variant calling workflow processing. The system uses novel architecture and algorithms to match against partial reference genomes to exploit smaller memory sizes which are typically available in tiny processing systems. Extensive tests on a standard benchmark data-set (NA12878 Illumina platinum genome) confirm that the time consumed for the data transfer and completing variant calling workflow on SWARAM was competitive to that of a 32-core Intel Xeon server with similar accuracy, but costs less than a fifth, and consumes less than 40% of the energy of the server system. The original scripts and code we developed for executing the variant calling workflow on SWARAM are available in the associated Github repository https://***/Rammohanty/swaram.

关键词： Genome alignment variant calling genetic analysis embedded system ARM DNA analysis energy efficient system portable genome analysis

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Special Session: Future Automotive systems Design: Research Challenges and Opportunities

Special Session: Future Automotive Systems Design: Research ...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Saidi, Selma Steinhorst, Sebastian Hamann, Arne Ziegenbein, Dirk Wolf, Marko Hamburg Univ Technol Hamburg Germany Tech Univ Munich Munich Germany Robert Bosch GmbH Renningen Germany ESCRYPT GmbH Munich Germany

ISBN: (纸本)9781538655627

Automotive systems are currently undergoing a radical shift in the way they are designed, implemented and deployed. Such changes impose an increased complexity and a high number of requirements in order to be more automated, connected, dependable and cost-effective. This raises several challenges that the embedded systems community has to face, encountered at different stages of systems development from modeling and design to software/hardware deployment and validation. This paper discusses current industrial trends and open problems in the hardware and software design of automotive systems, dictating rigorous constraints in terms of safety, real-time capabilities and security which have to be considered in future automotive systems design.

关键词： Automotive engineering software Computer architecture hardware system analysis and design Market research Safety

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Work-in-Progress: AMVP - A High Performance Virtual Platform using Parallel systemC for Multicore ARM Architectures

Work-in-Progress: AMVP - A High Performance Virtual Platform...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Weinstock, Jan Henrik Bucs, Robert Lajos Walbroel, Florian Leupers, Rainer Ascheid, Gerd Rhein Westfal TH Aachen Aachen Germany

ISBN: (纸本)9781538655627

This paper presents AMVP - a systemC based simulator for ARM multicore platforms designed as a tool for early SW development during platform bring-up. It uses a parallel systemC simulation approach to counter the performance slowdown incurred when simulating multi-processor designs. AMVP is sufficiently detailed to support running and debugging unmodified SW images of popular benchmark applications and modern OS kernels like Linux.

关键词： Electronic system Level Parallel Discrete Event Simulation Parallel systemC Simulation

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Work-in-Progress: Co-Design of Security-Critical Real-Time systems to Prevent Fault Injection Attacks

Work-in-Progress: Co-Design of Security-Critical Real-Time S...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Jiang, Wei Xiu, Liugen Zhan, Jinyu Jiang, Ke Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China Veoneer Res & Engn Dept Stockholm Sweden

ISBN: (纸本)9781538655627

We present a system-level co-design approach for security-critical real-time systems to resist fault injection attack. We focus on protecting the encryption/decryption of confidential messages over the internal communication in distributed real-time systems. To achieve the goal, we identify ten mechanisms of Fault Detection and Correction (FDC) and measure their corresponding time overheads and hardware overheads. We then make efforts to search for the best FDC schemes for protecting the message communication without violating the application deadline and hardware budget. We propose an efficient heuristic based on multi-objective evolutionary algorithms, which obtains better solutions with lower time complexity. Experiments demonstrate the superiority of the proposed technique.

关键词： Field programmable gate arrays Task analysis Cryptography Real-time systems Fault detection Resists

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Work-in-Progress: Hierarchical Ensemble Learning for Resource-Aware FPGA Computing

Work-in-Progress: Hierarchical Ensemble Learning for Resourc...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Wang, Hongfei Li, Jianwen He, Kun Cai, Wenjie Huazhong Univ Sci & Technol Sch Comp Sci & Technol Wuhan Peoples R China

ISBN: (纸本)9781538655627

Recent years witness the rapid development in hardware/software codesign that integrates machine learning (ML) models with hardware systems [1]–[4]. Despite the booming trend in building neuromorphic computing systems [2], decision trees still attract much attention in ML communities, from both software [5], [6] and hardware [1], [7], [8] approaches. A single tree model may not be as accurate as desired. One effective way to remedy this is to apply ensemble methods [5]–[7], [9]–[11], such as the Random Forest (RF) [5]. Larger tree ensembles typically improve accuracy, but demand more computation resources, especially for hardware implementation. Many methods have been proposed to address this issue. The motivation arouses from the fact that tree models usually demands much less computation resource comparing to neural networks, making them extremely potential for wearable devices and embedded systems at the edge nodes of the IoT [7], [11], [12]. Moreover, due to their inherent structures, tree ensembles are ideal for exploiting the computational parallelism on FPGA [1], [4], [7]–[9], [11], [13].

关键词： Radio frequency Vegetation hardware Field programmable gate arrays Forestry Minimization Computational modeling

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Work-in-Progress: Equivalence of Transformations of Synchronous Data Flow Graphs

Work-in-Progress: Equivalence of Transformations of Synchron...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Zhu, Xue-Yang Chinese Acad Sci State Key Lab Comp Sci Inst Software Beijing Peoples R China

ISBN: (纸本)9781538655627

Synchronous data flow graphs (SDFGs) are widely used to model digital signal processing (DSP) algorithms and streaming applications. Any valid SDFG can be converted to an equivalent homogenous SDFG (HSDFG). Retiming and unfolding are important graph transformation techniques for performance optimization of SDFGs. In this paper, we review the relationship among the three transformation techniques and reveal the equivalence of the combinations of them. The equivalence makes it possible to analyze and optimize SDFGs directly, without carrying out the explicit conversion procedures which are usually time and space-consuming.

关键词： IP networks Computational modeling Signal processing algorithms Processor scheduling Digital signal processing Optimization

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