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DevScope: A Nonintrusive and Online Power Analysis Tool for Smartphone hardware Components 12

DevScope: A Nonintrusive and Online Power Analysis Tool for ...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Jung, Wonwoo Kang, Chulkoo Yoon, Chanmin Kim, Dongwon Cha, Hojung Yonsei Univ Dept Comp Sci Seoul 120749 South Korea

ISBN: (纸本)9781450314268

Smartphone power modeling is an important technique for users, application developers, and hardware manufacturers to build energy-aware systems. Compared to traditional offline techniques that use external power measurement devices, the online approach uses a built-in BMU (Battery Monitoring Unit), which has the advantage of generating a dynamic power model. However, the very low update rate of a BMU is an issue for online power modeling. In this paper, we introduce an autonomous power modeling tool for smartphones called DevScope, which overcomes the limitations of BMU-based online power modeling. DevScope controls components according to the BMU update rate, and derives the component power model automatically by analyzing the changes of power state. With DevScope, we construct an online and automatic power modeling that reflects both the diversity of users' environments and smartphone hardware complexity. By evaluating the scheme with various smartphones and configurations, we show that DevScope, indeed, generates a flexible and accurate power model.

关键词： Smartphone Power Analysis Power Modeling Battery Monitoring Unit

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WiderFrame: An Automatic Customization Framework for Building CNN Accelerators on FPGAs: Work-in-Progress

WiderFrame: An Automatic Customization Framework for Buildin...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Gong, Lei Wang, Chao Li, Xi Zhou, Xuehai Univ Sci & Technol China Sch Comp Sci & Technol Hefei Peoples R China

ISBN: (纸本)9781728191980

hardware acceleration based on FPGA has been an important means to improve the computational efficiency of CNNs. However, due to the increasing complexity of the modern CNNs and the diversity of neural computing engines, it is challenging to make full use of FPGAs' customizability for efficient and fast accelerator designs. This paper proposes Wider-Frame, an automatic customization framework for building CNN accelerators on FPGA. Towards fully exploiting the customizability of FPGA for specific computing scenarios, WiderFrame integrates a systematical design space exploration methodology considered with different parallel and data reuse manners among various neural computing engines, a parameterized configurable code template with a set of macro instruction mechanism, for automatically generating the underlying hardware units and the control flow. Evaluation results show that WiderFrame can well support more CNN types, and can improve the performance and the energy efficiency up to 1.25x and 1.68x compared with state-of-the-art frameworks.

关键词： FPGA CNN hardware accelerator Framework

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A novel deadlock avoidance algorithm and its hardware implementation

A novel deadlock avoidance algorithm and its hardware implem...

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Second IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004

作者： Lee, Jaehwan Mooney III, Vincent John Georgia Institute of Technology Atlanta GA United States

ISBN: (纸本)1581139373

This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provides a mechanism for very fast and automatic deadlock avoidance in MultiProcessor system-on-a-Chip (MP-SoC) with multiple (e.g., 10) processing elements and multiple (e.g., 40) resources. The DAU avoids deadlock by not allowing any grant or request that leads to a deadlock. In case of livelock, the DAU asks one of the processes involved in the livelock to release resource(s) so that the livelock can also be resolved. We simulated two realistic examples that can benefit from the DAU, and demonstrated that the DAU not only avoids deadlock in a few clock cycles but also achieves a 37% speed-up of application execution time over avoiding deadlock in software. Finally, the SoC area overhead due to the DAU is small, under 0.01% in our example.

关键词： Computer hardware

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An Efficient Technique for Computing Importance Measures in Automatic Design of Dependable Embedded systems 14

An Efficient Technique for Computing Importance Measures in ...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Aliee, Hananeh Glass, Michael Khosravi, Faramarz Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Erlangen Germany

ISBN: (纸本)9781450330510

Importance measure analysis judges the relative importance of components in a system and reveals how each component contributes to the system reliability. In the design of large and complex systems, importance measure analysis can therefore be employed to guide an optimization tool which design decisions to investigate to gain higher reliability. While previous research has mainly concentrated on developing analytical importance measure techniques, the automatic and frequent computing of importance measures as required in the context of design space exploration has got very few, if any attention. This paper presents a highly efficient technique to compute the reliability and structural importance measures of components of a system. The proposed technique considers the reliability of a system implementation and subsequently analyzes the importance measures of its components based on a state-of-the-art Monte Carlo simulation. The technique can therefore estimate the importance measures of all components concurrently, highly improving the performance of the computation compared, e.g., to the well-known Birnbaum approach by the factor of 2n with n being the number of components. Moreover, we show how this algorithm can be extended to support importance measure analysis in the existence of transient faults which is essential since in future systems, transient faults are expected to cause relatively more failures than permanent faults. We integrated the proposed analysis approach in an existing multi-objective local-search algorithm that is part of an automatic system-level design space exploration which seeks for system implementations with highest reliability at lowest possible cost. Experimental results show that the proposed algorithm performs efficiently with negligible imprecision, even for large real world examples.

关键词： importance sampling search problems Birnbaum approach Monte Carlo simulation automatic design automatic system-level design space exploration complex system dependable embedded systems importance measure analysis importance measure techniques large system multiobjective local-search algorithm optimization tool permanent fault structural importance measures system implementation system reliability transient fault Algorithm design and analysis Boolean functions hardware Reliability engineering Space exploration Transient analysis Computer-Aided Design transient fault system implementation permanent fault Space Exploration Algorithm design and analysis Reliability engineering tabu search Complex systems Transient analysis Boolean functions importance sampling Monte Carlo technique Computer hardware

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system factorization in codesign: A case study of the use of formal techniques to achieve hardware-software decomposition

System factorization in codesign: A case study of the use of...

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Proceedings of the 1993 IEEE international conference on Computer Design: VLSI in Computers & Processors

作者： Bose, Bhaskar Tuna, M. Esen Johnson, Steven D. Indiana Univ Bloomington United States

ISBN: (纸本)0818642300

A major element of codesign is the task of decomposing a design in order to target some of its components to hardware and some to software while maintaining the integrity of the execution model. We illustrate how a previously developed algebraic technique we call system factorization adapts to this notion of decomposition. As an example, we describe how the mechanization of system factorization was used in the formal derivation of an implementation of Hunt's FM9001 microprocessor description using the DDD design derivation system. This case study demonstrates the benefits to system-level design in combining an executable modeling language, its associated formal-reasoning systems, hardware synthesis tools, and a hardware development platform in an integrated prototyping environment.

关键词： Integrated circuit layout

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Specification and OS-based implementation of self-adaptive, hardware/software embedded systems 08

Specification and OS-based implementation of self-adaptive, ...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Eustache, Yvan Diguet, Jean-Philippe Université Européenne de Bretagne UBS LabSTICC Lorient France

ISBN: (纸本)9781605584706

This paper presents our solution for specifying and imple-menting self-adaptivness within an OS-based and reconfig-urable embedded system according to objectives such as qual-ity of service (QoS), performance or power consumption. More precisely, we detail our approach to separate, at runtime, application-specific decisions and hardware/software imple-mentation decisions at system level. The first ones are re-lated to the control of the efficiency of applications, they are specified in Local Configuration Managers (LCM) based on the knowledge of application engineers. The second ones are generic and address the choice between various hardware and software implementations according to observations of the gap between online measurements and objectives set by the user, these decisions are implemented in the Global Con-figuration Manager (GCM) as an adaptive close-loop model. We have designed a video tracking application on an FPGA to demonstrate the effectiveness of our solution, results are given for a system built around a NIOS soft-core with μCOS II RTOS and new services for managing hardware and soft-ware tasks transparently. Copyright 2008 ACM.

关键词： Embedded systems

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Work-in-Progress: A concept of a hardware design environment with the functional language Elixir

Work-in-Progress: A concept of a hardware design environment...

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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Takase, Hideki Matsui, Kentaro Ueno, Yoshihiro Mori, Masakazu Hisae, Yuki Yamazaki, Susumu Kyoto Univ Sakyo Ku Kyoto Japan Delight Syst Co Ltd Chuo Ku Fukuoka Japan Karabiner Technol Inc Chuo Ku Fukuoka Japan Univ Kitakyushu Wakamatsu Ku Kitakushu Japan JST PRESTO Tokyo Japan

ISBN: (纸本)9781450369237

The functional language Elixir is designed to be effective for the application. One of the most considerable feature of Elixir is that it is easy to realize the parallel processing with the standard library, such as Flow. In this paper, we study a design environment for hardware circuits using Elixir as a design language. We propose a synthesize flow for data flow hardware on the FPGA from the native Elixir code. Our method synthesizes functional equivalence circuits from the description of Enum and Flow in Elixir, which are libraries for direct manipulation and parallel processing of data collection in Elixir. Data flow is implemented base on the pipeline operator vertical bar> which connects the processing relation of the function by the data processing order. To realize a hardware design environment by Elixir, this paper shares current status of our implementation.

关键词： Elixir functional language high-level synthesis

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Statistical approach in a system level methodology to deal with process variation 10

Statistical approach in a system level methodology to deal w...

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Sanz Pineda, Concepción Prieto, Manuel Gómez, José Ignacio Tenllado, Christian Catthoor, Francky Dpto. de Arquitectura de Computadores Y Automática Universidad Complutense de Madrid Madrid 28040 Spain Inter-University Microelectronics Center IMEC Leuven 3001 Belgium

ISBN: (纸本)9781605589053

The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of both energy consumption and performance. In this context, developing variation aware design methodologies becomes a must. These techniques should provide better performance-energy balances while the percentage of faulty products keeps controlled. Furthermore, it would be advisable to consider adaptations of the system during lifetime, in order to provide robustness against ageing. In this paper we propose a design approach which tackles process variation on the memory system by using multimode memories. At design time we perform a heuristic exploration using probabilistic models of these memories, which generates a set of system configurations that minimize energy consumption for a given set of timing constraints. The percentage of systems that will satisfy these deadlines, even under process variation, is taken as a design parameter. Additionally, if system monitors are available, a setup stage optimizes the initial set of configurations for the actual memory parameters. Our simulations show that this methodology provides significant energy savings while still meeting timing constraints. © 2010 ACM.

关键词： Energy utilization

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Complex task activation schemes in system level performance analysis

Complex task activation schemes in system level performance ...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Haid, Wolfgang Thiele, Lothar Zurich Switzerland

ISBN: (纸本)9781595938244

The design and analysis of today's complex real-time systems requires advanced methods. Due to ever growing functionality, hardware complexity and component interaction, applying traditional methods like HW/SW cosimulation is getting increasingly difficult. On the other hand, analytic approaches have proven their usefulness and efficiency for system analysis when end-to-end performance figures like delay, throughput and memory consumption are requested. One of the main drawbacks of these methods is the limited set of systems that can be analyzed with high accuracy: Only simple models for task interaction and task semantics can be used. In this paper, we extend existing methods for analyzing heterogeneous multiprocessor systems such that (a) nonpreemptive scheduling policies, (b) complex activation schemes for tasks and (c) conditional behavior of task executions can be modeled and analyzed. We demonstrate the usefulness of the proposed approach in a case study. Copyright 2007 ACM.

关键词： software architecture

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Scalable and Realistic Benchmark synthesis for Efficient NoC Performance Evaluation: A Complex Network Analysis Approach 16

Scalable and Realistic Benchmark Synthesis for Efficient NoC...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Xue, Yuankun Bogdan, Paul Univ Southern Calif 3740 McClintock Ave Los Angeles CA 90007 USA

ISBN: (纸本)9781450344838

The complexity of the design-space exploration of large-scale NoCs is exacerbated not only by the ever-increasing number of cores, but also by the increased runtime uncertainties in both the scale and task structure of the emerging applications. Consequently, it is crucial to develop rigorous mathematical frameworks for capturing the task dependencies of varied applications to foster the generation of realistic benchmarks that can guide the NoC design. However, the current NoC benchmark suites either lack portability and poorly scale as they require intensive development efforts on specific architectures and simulation time, or are synthesized based on purely stochastic models that are disconnected with real applications, which may easily lead to biased and/or delayed design choices. To overcome these drawbacks, we propose a benchmark synthesis framework that i) not only allows extraction of dynamical task dependencies of the application and synthesize traffic workloads spatio-temporally consistent with realistic traffic behavior, ii) but can also be easily scaled by the proposed complex network inspired algorithm for large benchmark generation while preserving key structural features that governs application communication behaviors. We validate the proposed framework on a large-scale simulation environment by running a set of real applications. Experimental results show that the synthesized benchmarks respect the traffic patterns of the original applications and preserve key features of application task structures.

关键词： Network-on-chip

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