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Compositional Design of Multi-Robot systems Control software on ROS

ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 71-71页

作者： Spellini, Stefano Lora, Michele Fummi, Franco Chattopadhyay, Sudipta Univ Verona Dept Comp Sci Str Grazie 15 I-37134 Verona Italy Singapore Univ Technol & Design ISTD 8 Somapah Rd Singapore 487372 Singapore

This paper presents a methodology that relies on Assume-Guarantee Contracts to decompose the problem of synthesizing control software for a multi-robot system. Initially, each contract describes either a component (e.g., a robot) or an aspect of the system. Then, the design problem is decomposed into different synthesis and verification sub-problems, allowing to tackle the complexity involved in the design process. The design problem is then recomposed by exploiting the rigorousness provided by contracts. This allows us to achieve system-level simulation capable to be used for validating the entire design. Once validated, the software synthesized during the process can be integrated into Robot Operating system (ROS) nodes and executed using state-of-the-practice packages and tools for modern robotic systems. We apply the methodology to generate a control strategy for an autonomous goods transportation system. Our results show a massive reduction of the time required to obtain automatically the control software implementing a multi-robot mission.

关键词： Contract-based design robotic operating system

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Treble: Fast software Updates by Creating an Equilibrium in an Active software Ecosystem of Globally Distributed Stakeholders

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 104-104页

作者： Yim, Keun Soo Malchev, Iliyan Hsieh, Andrew Burke, Dave Google 1600 Amphitheatre Pkwy Mountain View CA 94043 USA

This paper presents our experience with Treble, a two-year initiative to build the modular base in Android, a Java-based mobile platform running on the Linux kernel. Our Treble architecture splits the hardware independent core framework written in Java from the hardware dependent vendor implementations (e.g., user space device drivers, vendor native libraries, and kernel written in C/C++). Cross-layer communications between them are done via versioned, stable inter-process communication interfaces whose backward compatibility is tested by using two API compliance suites. Based on this architecture, we repackage the key Android software components that suffered from crucial post-launch security bugs as separate images. That not only enables separate ownerships but also independent updates of each image by interested ecosystem entities. We discuss our experience of delivering Treble architectural changes to silicon vendors and device makers using a yearly release model. Our experiments and industry rollouts support our hypothesis that giving more freedom to all ecosystem entities and creating an equilibrium are a transformation necessary to further scale the world largest open source ecosystem with over two billion active devices.

关键词： Open source ecosystem software architecture software update

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Work-in-Progress: Runtime Requirements Monitoring for State-based hardware

Work-in-Progress: Runtime Requirements Monitoring for State-...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Minjun Seo Roman Lysecky Department of Electrical and Computer Engineering University of Arizona Tucson AZ USA

This paper presents a requirements-driven methodology enabling efficient runtime monitoring of hardware in embedded systems. We present a novel method for extracting hardware verification requirements from state-based hardware models to construct a hierarchical runtime monitoring graph (HRMG) that can be efficiently used at runtime to verify correctness.

关键词： Monitoring hardware Runtime Embedded systems Timing Unified modeling language

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Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 76-76页

作者： Dugo, Alexy Torres Aurora Lefoul, Jean-Baptiste De Magalhaes, Felipe Gohring Assal, Dahman Nicolescu, Gabriela Ecole Polytech Montreal 2900 Boul Edouard Montpetit Montreal PQ Canada Mannarino Syst & Software Inc Montreal PQ Canada

Avionic software is the subject of stringent real time, determinism and safety constraints. software designers face several challenges, one of them being the interferences that appear in common situations, such as resource sharing. The interferences introduce non-determinism and delays in execution time. One of the main interference prone resources are cache memories. In single-core processors, caches comprise multiple private levels. This breaks the isolation principle imposed by avionic standards, such as the ARINC-653. This standard defines partitioned architectures where one partition should never directly interfere with another one. In cache-based architectures, one partition can modify the cache content of another partition. In this paper, we propose a method based on cache locking to reduce the non-determinism and the contention on lower level memories while improving the time performances.

关键词： Critical systems ARINC-653 interference cache locking aerospace

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Synterface: Efficient Chip-to-World Interfacing for Flow-Based Microfluidic Biochips Using Pin-Count Minimization

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 54-54页

作者： Sridhar, Aditya Ibrahim, Mohamed Chakrabarty, Krishnendu Duke Univ Dept Elect & Comp Engn 130 Hudson Hall Durham NC 27708 USA

Flow-based microfluidic biochips can be used to perform bioassays by manipulating a large number of on-chip valves. These biochips are increasingly used today for biomolecular recognition, single-cell screening, and point-of-care disease diagnostics, and design-automation solutions for flow-based microfluidics enable the mapping and optimization of bimolecular protocols and software-based valve control. However, a key problem that has not received adequate attention is chip-to-world interfacing, which requires the use of off-chip control equipment to provide control signals for the on-chip valves. This problem is exacerbated by the increase in the number of valves as chips get more complex. To address the interfacing problem, we present an efficient pin-count minimization (synthesis) problem, referred to as Synterface, which uses on-chip microfluidic logic gates and optimization based on concepts from linear algebra. We present results to show that Synterface significantly reduces pin-count and simplifies the external interface for flow-based microfluidics.

关键词： Microfluidic biochips chip-to-world interfacing synthesis logic gates

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Work-in-Progress: hardware Implementation of a Multi-Mode-Aware Mixed-Criticality Scheduler

Work-in-Progress: Hardware Implementation of a Multi-Mode-Aw...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sena Hounsinou Aishwarya Vasu Harini Ramaprasad Southern Illinois University Carbondale University of North Carolina Charlotte

To minimize size, weight, power and cost, the industry aims at consolidating different criticality applications on the same hardware platform. In such a mixed-criticality environment, it is challenging to contain the overhead due to potential mode changes under overload conditions. Traditional scheduler implementation at the software level introduces additional overheads due to timer interrupt processing and context switching. To minimize overall software overhead and to improve timing predictability, in this paper, we propose an implementation of the mixed-criticality scheduler in the hardware that is capable of detecting task-overruns and making mode transitions seamlessly.

关键词： Task analysis hardware Real-time systems Monitoring Registers software Processor scheduling

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Special Session: Future Automotive systems Design: Research Challenges and Opportunities

Special Session: Future Automotive Systems Design: Research ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Selma Saidi Sebastian Steinhorst Arne Hamann Dirk Ziegenbein Marko Wolf Hamburg University of Technology Hamburg Germany Technical University of Munich Munich Germany Robert Bosch GmbH Renningen Germany ESCRYPT GmbH Munich Germany

Automotive systems are currently undergoing a radical shift in the way they are designed, implemented and deployed. Such changes impose an increased complexity and a high number of requirements in order to be more automated, connected, dependable and cost-effective. This raises several challenges that the embedded systems community has to face, encountered at different stages of systems development from modeling and design to software/hardware deployment and validation. This paper discusses current industrial trends and open problems in the hardware and software design of automotive systems, dictating rigorous constraints in terms of safety, real-time capabilities and security which have to be considered in future automotive systems design.

关键词： Automotive engineering software Computer architecture hardware system analysis and design Market research Safety

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Work-in-Progress: WinoNN: Optimising FPGA-based Neural Network Accelerators using Fast Winograd Algorithm

Work-in-Progress: WinoNN: Optimising FPGA-based Neural Netwo...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Xuan Wang Chao Wang Xuehai Zhou School of Computer Science and Technology University of Science and Technology of China Hefei China

In this paper, we present WinoNN, which utilizes fast Winograd algorithm to optimize FPGA-based neural network accelerators. In particular, Winograd algorithm effectively reduces the resource occupation of FPGA, as well as boosts the system speedup, especially for embedded and mobile devices. The main contributions of this paper include implementation of single-channel convolution module, implementation of multi-channel convolution module, deployment and performance test on FPGA hardware platform. We use LeNet-5 as a case study, which demonstrates the performance of WinoNN is significantly better than the general ARM Cortex A series processors.

关键词： Convolution Field programmable gate arrays Convolutional neural networks Performance evaluation hardware Kernel

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Work-in-Progress: Dynamic Data Management for Automotive ECUs with Hybrid RAM-NVM Memory

Work-in-Progress: Dynamic Data Management for Automotive ECU...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jinyu Zhan Junhuan Yang Wei Jiang Yixin Li School of Information & Software Engineering University of Electronic Science & Technology of China China

Non-Volatile Memory (NVM) can be utilized to improve performance of automotive electronic systems, but frequent writings on NVM will decrease its lifetime. In this paper, we propose a Vehicle Dynamic Data Management (VDDM) scheme, which can distinguish the hot or cold data generated by vehicle Electronic Control Units (ECUs) and sensors, and manage the data to reduce the writing operations on NVM of the hybrid main memory. Experimental results show that VDDM can significantly reduce writing operations and prolong lifetime of NVM compared with other approaches.

关键词： Nonvolatile memory Random access memory Writing Memory management Vehicle dynamics Automotive electronics

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Work-in-Progress: Hierarchical Ensemble Learning for Resource-Aware FPGA Computing

Work-in-Progress: Hierarchical Ensemble Learning for Resourc...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hongfei Wang Jianwen Li Kun He Wenjie Cai School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Recent years witness the rapid development in hardware/software codesign that integrates machine learning (ML) models with hardware systems [1]-[4]. Despite the booming trend in building neuromorphic computing systems [2], decision trees still attract much attention in ML communities, from both software [5], [6] and hardware [1], [7], [8] approaches. A single tree model may not be as accurate as desired. One effective way to remedy this is to apply ensemble methods [5]-[7], [9]-[11], such as the Random Forest (RF) [5]. Larger tree ensembles typically improve accuracy, but demand more computation resources, especially for hardware implementation. Many methods have been proposed to address this issue. The motivation arouses from the fact that tree models usually demands much less computation resource comparing to neural networks, making them extremely potential for wearable devices and embedded systems at the edge nodes of the IoT [7], [11], [12]. Moreover, due to their inherent structures, tree ensembles are ideal for exploiting the computational parallelism on FPGA [1], [4], [7]-[9], [11], [13].

关键词： Radio frequency Vegetation hardware Field programmable gate arrays Forestry Minimization Computational modeling

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