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An Ultra-Low Energy Human Activity Recognition Accelerator for Wearable Health Applications

ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 49-49页

作者： Bhat, Ganapati Tuncel, Yigit An, Sizhe Lee, Hyung Gyu Ogras, Umit Y. Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Daegu Univ Sch Comp & Commun Engn Daegu 38453 South Korea

Human activity recognition (HAR) has recently received significant attention due to its wide range of applications in health and activity monitoring. The nature of these applications requires mobile or wearable devices with limited battery capacity. User surveys show that charging requirement is one of the leading reasons for abandoning these devices. Hence, practical solutions must offer ultra-low power capabilities that enable operation on harvested energy. To address this need, we present the first fully integrated custom hardware accelerator (HAR engine) that consumes 22.4 mu J per operation using a commercial 65 nm technology. We present a complete solution that integrates all steps of HAR, i.e., reading the raw sensor data, generating features, and activity classification using a deep neural network (DNN). It achieves 95% accuracy in recognizing 8 common human activities while providing three orders of magnitude higher energy efficiency compared to existing solutions.

关键词： Human activity recognition wearable electronics flexible hybrid electronics hardware accelerator low-power design health monitoring

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Work-in-Progress: On Leveraging Approximations for Exact system-level Design Space Exploration

Work-in-Progress: On Leveraging Approximations for Exact Sys...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Kai Neubauer Christian Haubelt Philipp Wanko Torsten Schaub University of Rostock Germany University of Potsdam Germany

In order to find good design points for embedded systems, an efficient exploration of the design space is imperative. The ever-increasing complexity of embedded systems, however, results in a deterioration of the overall exploration performance. The DSE essentially consists of two parts: (1) the search for feasible solutions and (2) the evaluation of found feasible solutions. While the search has been massively improved by ASPmT-based strategies, the evaluation emerges as the main bottleneck. Tragically, evaluating bad solutions takes as much time as evaluating good ones. Hence, in this paper we study the utilization of approximations in the evaluation process integrated in an ASPmT-based DSE to identify bad solutions more quickly while still retaining the exact Pareto-front.

关键词： Estimation Space exploration Linear programming system-level design Embedded systems Filtering theory Search problems

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Work-in-Progress: Co-Design of Security-Critical Real-Time systems to Prevent Fault Injection Attacks

Work-in-Progress: Co-Design of Security-Critical Real-Time S...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Wei Jiang Liugen Xiu Jinyu Zhan Ke Jiang School of Information & Software Engineering University of Electronic Science & Technology of China China Research and Engineering Department Veoneer Sweden

We present a system-level co-design approach for security-critical real-time systems to resist fault injection attack. We focus on protecting the encryption/decryption of confidential messages over the internal communication in distributed realtime systems. To achieve the goal, we identify ten mechanisms of Fault Detection and Correction (FDC) and measure their corresponding time overheads and hardware overheads. We then make efforts to search for the best FDC schemes for protecting the message communication without violating the application deadline and hardware budget. We propose an efficient heuristic based on multi-objective evolutionary algorithms, which obtains better solutions with lower time complexity. Experiments demonstrate the superiority of the proposed technique.

关键词： Field programmable gate arrays Task analysis Cryptography Real-time systems Fault detection Resists

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Work-in-Progress: A Chip-Level Security Framework for Assessing Sensor Data Integrity

Work-in-Progress: A Chip-Level Security Framework for Assess...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Taimour Wehbe Vincent J. Mooney David C. Keezer Georgia Institute of Technology Atlanta Georgia USA

The continuously increasing inter-connectivity of sensor nodes that form the basis of the Internet-of-Things results in new avenues of attack exploitable by adversaries to maliciously modify data captured by these nodes. In this work, we present a framework for detecting malicious hardware alterations that attempt to attack state-of-the-art microchips that form these sensor nodes. Specifically, we focus on extremely small hardware Trojans (HTs) that attempt to modify sensor data right away as the data is received on a state-of-the-art chip fabricated in an untrusted facility. We present a dual-chip approach composed of an untrusted state-of-the-art prover chip and a trusted verifier chip, where the verifier continuously challenges the prover at run-time to ensure correct operation and assess the integrity of the captured data. Our preliminary analysis of the proposed mechanism shows that HT attacks anywhere on the untrusted state-of-the-art chip are detected and flagged preventing maliciously altered data to be transmitted out of the sensor node.

关键词： hardware Trojan horses Integrated circuits Data integrity Embedded systems Drugs

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Work-in-Progress: Towards the Application of Flask Security Architecture to SoC Design 12

Work-in-Progress: Towards the Application of Flask Security ...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hategekimana, Festus Bobda, Christophe Univ Arkansas Fayetteville AR 72701 USA

ISBN: (纸本)9781450351850

In this work, we explore a security reference monitor (RM) design which borrows from the Flask security architecture. Our RM design goal is to achieve complete mediation by checking and verifying the authority and the authenticity of every access to every system object in systems-on-chip (SoCs). Access decisions are administered by a security logic "server" implemented as an extension of the peripheral bus. Initial results show a minimal increase in resource overhead and no significant impact on the performance.

关键词： systems-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs) Trojan hardware sandbox Secure Execution Component Authentication Process

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SWARAM: Portable Energy and Cost Efficient Embedded system for Genomic Processing

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 61-61页

作者： Mohanty, Ram Prasad Gamaarachchi, Hasindu Lambert, Andrew Parameswaran, Sri Univ New South Wales Canberra ACT 2612 Australia Univ New South Wales Sydney NSW 2052 Australia

Treatment of patients using high-quality precision medicine requires a thorough understanding of the genetic composition of a patient. Ideally, the identification of unique variations in an individual's genome is needed for specifying the necessary treatment. Variant calling workflow is a pipeline of tools, integrating state of the art software systems aimed at alignment, sorting and variant calling for the whole genome sequencing (WGS) data. This pipeline is utilized for identifying unique variations in an individual's genome (compared to a reference genome). Currently, such a workflow is implemented on high-performance computers (with additional GPUs or FPGAs) or in cloud computers. Such systems are large, have a high cost, and rely on the internet for genome data transfer which makes the system unusable in remote locations unequipped with internet connectivity. It further raises privacy concerns due to processing being carried out in a different facility. To overcome such limitations, in this paper, for the first time, we present a cost-efficient, offline, scalable, portable, and energy-efficient computing system named SWARAM for variant calling workflow processing. The system uses novel architecture and algorithms to match against partial reference genomes to exploit smaller memory sizes which are typically available in tiny processing systems. Extensive tests on a standard benchmark data-set (NA12878 Illumina platinum genome) confirm that the time consumed for the data transfer and completing variant calling workflow on SWARAM was competitive to that of a 32-core Intel Xeon server with similar accuracy, but costs less than a fifth, and consumes less than 40% of the energy of the server system. The original scripts and code we developed for executing the variant calling workflow on SWARAM are available in the associated Github repository https://***/Rammohanty/swaram.

关键词： Genome alignment variant calling genetic analysis embedded system ARM DNA analysis energy efficient system portable genome analysis

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High-Level synthesis of Approximate Designs under Real-Time Constraints

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 59-59页

作者： Leipnitz, Marcos T. Nazar, Gabriel L. Univ Fed Rio Grande do Sul Informat Inst Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

The adoption of High-Level synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

关键词： High-level synthesis approximate computing worst-case execution time design space exploration

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Deriving Equations from Sensor Data Using Dimensional Function synthesis

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 84-84页

作者： Wang, Youchao Willis, Sam Tsoutsouras, Vasileios Stanley-Marbell, Phillip Univ Cambridge 9 JJ Thomson Ave Cambridge CB3 0FA England

We present a new method for deriving functions that model the relationship between multiple signals in a physical system. The method, which we call dimensional function synthesis, applies to data streams where the dimensions of the signals are known. The method comprises two phases: a compile-time synthesis phase and a subsequent calibration using sensor data. We implement dimensional function synthesis and use the implementation to demonstrate efficiently summarizing multi-modal sensor data for two physical systems using 90 laboratory experiments and 10 000 synthetic idealized measurements. We evaluate the performance of the compile-time phase of dimensional function synthesis as well as the calibration phase overhead, inference latency, and accuracy of the models our method generates. The results show that our technique can generate models in less than 300 ms on average across all the physical systems we evaluated. When calibrated with sensor data, our models outperform traditional regression and neural network models in inference accuracy in all the cases we evaluated. In addition, our models perform better in training latency (over 8660x improvement) and required arithmetic operations in inference (over 34x improvement). These significant gains are largely the result of exploiting information on the physics of signals that has hitherto been ignored.

关键词： Machine learning dimensional analysis sensor data fusion

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Work-in-Progress: Furion: Alleviating Overheads for Deep Learning Framework On Single Machine

Work-in-Progress: Furion: Alleviating Overheads for Deep Lea...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Lihui Jin Chao Wang Lei Gong Chongchong Xu Yahui Hu Luchao Tan Xuehai Zhou University of Science and Technology of China

Deep learning has been successful at solving many kinds of tasks. hardware accelerators with high performance and parallelism have become mainstream to implement deep neural networks. In order to increase hardware utilization, multiple applications will share the same compute resource. However, different applications may use different deep learning frameworks and occupy different amounts of resources. If there are no scheduling platforms that are compatible with different frameworks, resources competition will result in longer response time, run out of memory, and other errors. When the resources of the system cannot satisfy all the applications at the same time, application switching overhead will be excessive without reasonable resource management strategy. In this paper, we propose Furion - a middleware alleviates overheads for deep learning framework on a single machine. Furion schedules tasks, overlaps the execution of different computing resource, and batches unknown inputs to increase the hardware accelerator utilization. It dynamically manages memory usage for each application to alleviate the overhead of application switching and make a complex model enable implement in a low-end GPU. Our experiment proved that Furion achieves 2.2x-2.7x speedup on the GTX1060.

关键词： hardware Task analysis Graphics processing units Switches Neural networks Throughput

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Enhanced Resilient Sensor Attack Detection Using Fusion Interval and Measurement History 18

Enhanced Resilient Sensor Attack Detection Using Fusion Inte...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Kang Yang Rui Wang Yu Jiang Chenxia Luo Yong Guan Xiaojuan Li Zhiping Shi College of Information Engineering Capital Normal University Beijing China School of Software Tsinghua University Beijing China

ISBN: (纸本)9781538655627

For the Cyber-Physical systems which are equipped with multiple sensors that measure the same physical variables, some of the sensors may be subject to malicious attacks and provide the wrong measurements to the controller, resulting in an unsafe state of the system. Although there are several methods for detecting sensor attacks, they may not work well when an attacker manipulates the sensor output very slightly or infrequently over a period of time, e.g., stealth attacks. To address this problem, we take the system dynamics model into account, and propose a novel sensor attack detection algorithm based on historical measurements and fusion intervals. The core idea is to build different fault models for different sensors, add a virtual sensor to use pairwise inconsistencies between two sensors to identify attacks. Finally, we validate the performance of the algorithm on real measurements obtained from the LEGO EV3 ground vehicle, and the results show that the proposed method outperforms state-of-the-art algorithm, especially for stealth attacks, with about 92% promotion in attack detection and identification rate.

关键词： Robot sensing systems Transient analysis Silicon Detectors Security Time measurement Cyber-physical systems

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