检索结果-内蒙古大学图书馆

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Jiang, Honglan Liu, Leibo Han, Jie Univ Alberta Edmonton AB Canada Tsinghua Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781450351850

The superior controllability of the cerebellum has motivated extensive interest in the development of computational cerebellar models. Many models have been applied to the motor control and image stabilization in robots. Often computationally complex, cerebellar models have rarely been implemented in dedicated hardware. Here, we propose an efficient hardware design for cerebellar models using approximate circuits with a small area and a low power. Leveraging the inherent error tolerance in the cerebellum, approximate adders and multipliers are carefully evaluated for implementations in an adaptive filter based cerebellar model to achieve a good tradeoff in accuracy and hardware usage. A saccade system, whose vestibulo-ocular reflex (VOR) is controlled by the cerebellum, is simulated to show the applicability and effectiveness of the proposed design. Simulation results show that the approximate cerebellar circuit achieves a similar accuracy as an exact implementation, but it saves area by 29.7% and power by 37.3%.

关键词： Cerebellar model approximate circuits multiplier adder

来源：评论

学校读者我要写书评

暂无评论

Keynote: Internet of Things or Threats? On Building Trust in IoT

Keynote: Internet of Things or Threats? On Building Trust in...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Markus Miettinen Ahmad-Reza Sadeghi System Security Lab Technische Universität Darmstadt Darmstadt Germany

The Internet of things (IoT) is rapidly emerging with the goal to connect the unconnected. Many new device manufacturers are entering the market of internet-connected appliances for smart homes and offices, ranging from motion sensors to virtual voice assistants. However, due to lack of security by design and flawed implementations we are facing significant security and privacy challenges specific to IoT, such as perilous IoT botnet attacks, and novel privacy threats caused by widespread installation of wireless sensors, actuators and smart home appliances even in the private setting of our homes. Unfortunately, basic security measures like properly encrypted communications does not protect against these threats. The massive scale of the IoT device population and enormous diversity of device hardware, operating systems, software frameworks and manufacturers makes it very difficult to establish standard IoT security and privacy-protecting solutions by simply applying known solutions, neither for per-device security architectures nor for network security measures. In particular, existing intrusion detection techniques to detect compromised IoT devices seem ineffective. In this talk, we will present our recent work on addressing various security and privacy challenges in the growing IoT landscape including industry collaborations. In particular, we focus on approaches for flexible management of security associations (pairing) among devices introduced into the user's trust domain as well as effectively and efficiently identifying these devices based on their inherent communication behavior and using these behavior patterns to automatically and reliably detect compromised IoT devices.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Remote Detection of Unauthorized Activity via Spectral Analysis 12

Work-in-Progress: Remote Detection of Unauthorized Activity ...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Karabacak, Fatih Ogras, Umit Ozev, Sule Arizona State Univ Sch ECEE Tempe AZ 85281 USA

ISBN: (纸本)9781450351850

Unauthorized hardware or firmware modifications, known as trojans, can steal information, drain the battery, or damage IoT devices. This paper presents a stand-off self-referencing technique for detecting unauthorized activity. The proposed technique processes involuntary electromagnetic emissions on a separate hardware, which is physically decoupled from the device under test. When the device enter the test mode, it runs a predefined application repetitively with a fixed period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operation bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicates the presence of unknown (unauthorized) activity. Experiments based on hardware measurements show that the proposed technique achieves close to 100% detection accuracy at up to 120 cm distance.

关键词： IoT Security hardware/Firmware Trojan Detection EM Emission

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Heterogeneous Redundancy to Address Performance and Cost in Multi-core SIMT 12

Work-in-Progress: Heterogeneous Redundancy to Address Perfor...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Naghashi, M. Mozafari, S. H. Hessabi, S. Sharif Univ Technol Tehran Iran McGill Univ Montreal PQ Canada

ISBN: (纸本)9781450351850

As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. In this work, we investigate adding heterogeneous hot redundancy (i.e., the architecture of redundant hot cores is diferent from the baseline cores) to improve the cost and performance of multicore single-instruction, multiple-thread (SIMT) architectures. We propose to utilize x86 out of order (OoO) cores as redundancy in SIMT processors. In this case, dice with unused functional redundancies can beneit from two types of processing cores (OoO and SM).

关键词： Manufacturability system-level design redundancy

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Exploring Fast and Slow Memories in HMP Core Types 12

Work-in-Progress: Exploring Fast and Slow Memories in HMP Co...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Donyanavard, Bryan Monazzah, Amir Mandi Hosseini Muck, Tiago Dutt, Nikil Univ Calif Irvine Irvine CA 92697 USA Sharif Univ Technol Tehran Iran

ISBN: (纸本)9781450351850

Studies have shown memory and computational needs vary independently across applications. Recent work has explored using hybrid memory technology (SRAM+NVM) in on-chip memories of multicore processors (CMPs) to support the varied needs of diverse workloads. Such works suggest architectural modifications that require supplemental management in the memory hierarchy. Instead, we propose to deploy hybrid memory in a manner that integrates seamlessly with the existing heterogeneous multicore (HMP) architectural model, and therefore does not require any architectural modification, simply the integration of different memory technologies on-chip. We evaluate platforms with a combination of fast (SRAM cache) and slow (STT-MRAM cache) core-types for mobile workloads.

关键词： SPM scratchpad Memory hardware/software memory management many-core architectures virtualization

来源：评论

学校读者我要写书评

暂无评论

Statistical Verification of Hyperproperties for Cyber-Physical systems

引用

ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 92-92页

作者： Wang, Yu Zarei, Mojtaba Bonakdarpour, Borzoo Pajic, Miroslav Duke Univ 100 Sci DrHudson Hall Rm 220 Durham NC 27708 USA Iowa State Univ 207 Atanasoff Hall Ames IA 50011 USA

Many important properties of cyber-physical systems (CPS) are defined upon the relationship between multiple executions simultaneously in continuous time. Examples include probabilistic fairness and sensitivity to modeling errors (i.e., parameters changes) for real-valued signals. These requirements can only be specified by hyperproperties. In this article, we focus on verifying probabilistic hyperproperties for CPS. To cover a wide range of modeling formalisms, we first propose a general model of probabilistic uncertain systems (PUSs) that unify commonly studied CPS models such as continuous-time Markov chains (CTMCs) and probabilistically parametrized Hybrid I/O Automata (P(2)HIOA). To formally specify hyperproperties, we propose a new temporal logic, hyper probabilistic signal temporal logic (HyperPSTL) that serves as a hyper and probabilistic version of the conventional signal temporal logic (STL). Considering the complexity of real-world systems that can be captured as PUSs, we adopt a statistical model checking (SMC) approach for their verification. We develop a new SMC technique based on the direct computation of significance levels of statistical assertions for HyperPSTL specifications, which requires no a priori knowledge on the indifference margin. Then, we introduce SMC algorithms for HyperPSTL specifications on the joint probabilistic distribution of multiple paths, as well as specifications with nested probabilistic operators quantifying different paths, which cannot be handled by existing SMC algorithms. Finally, we show the effectiveness of our SMC algorithms on CPS benchmarks with varying levels of complexity, including the Toyota Powertrain Control system.

关键词： Cyber-physical systems hyperproperties statistical model checking embedded control software

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: A Fast Online Sequential Learning Accelerator for IoT Network Intrusion Detection 12

Work-in-Progress: A Fast Online Sequential Learning Accelera...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Huang, Hantao Khalid, Rai Suleman Liu, Wenye Yu, Hao Nanyang Technol Univ Sch Elect & Elect Engn Singapore Singapore

ISBN: (纸本)9781450351850

Deployment of IoT devices for smart buildings and homes will offer a high level of comfortability with increased energy efficiency;but can also introduce potential cyber-attacks such as network intrusions via linked IoT devices. Due to the low-power and low-latency requirement to secure IoT network, traditional software based security system is not applicable. Instead, an embedded hardware-accelerator based data analytics is more preferred for network intrusion detection. In this paper, we propose an online sequential machine learning hardware accelerator to perform real-time network intrusion detection. A single hidden layer feedforward neural network based learning algorithm is developed with a least-squares solver realized on hardware. Experimental results on a single FPGA achieve a bandwidth of 409.6 Gbps with fast yet low-power network intrusion detection based on a number of benchmarks.

关键词： Intrusion detection hardware Training Field programmable gate arrays Benchmark testing Telecommunication traffic Computer architecture

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: A Unified Framework for Throughput Analysis of Synchronous Data Flow Graphs under Memory Constraints 12

Work-in-Progress: A Unified Framework for Throughput Analysi...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Zhu, Xue-Yang Chinese Acad Sci Inst Software State Key Lab Comp Sci Beijing 100190 Peoples R China

ISBN: (纸本)9781450351850

Streaming applications are often modeled with Synchronous data flow graphs (SDFGs). A proper analysis of the models is helpful to predict the performance of a system. In this paper, we focus on the throughput analysis of memory-constrained SDFGs (MC SDFGs), which needs to choose a memory abstraction that decides when the space of consumed data is released and when the required space is claimed. Different memory abstractions may lead to different achievable throughputs. The existing techniques, however, consider only a certain abstraction. If a model is implemented according to other abstractions, the analysis result may not truly evaluate the performance of the system. In this paper, we present a unified framework for throughput analysis of MC SDFGs for difference abstractions, aiming to provide evaluations matching up to the corresponding implementations.

关键词： Throughput Memory management Computational modeling Analytical models Electromagnetic compatibility Data models Flow graphs

来源：评论

学校读者我要写书评

暂无评论

Special Session Paper: Exploiting Quality-Energy Tradeoffs with Arbitrary Quantization

Special Session Paper: Exploiting Quality-Energy Tradeoffs w...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Moreau, Thierry Augusto, Felipe Howe, Patrick Alaghi, Armin Ceze, Luis Univ Washington Seattle WA 98195 USA Univ Estadual Campinas Campinas SP Brazil

ISBN: (纸本)9781450351850

Approximate computing aims to expose and exploit quality vs. efficiency tradeoffs to enable ever-more demanding applications on energy-constrained devices such as smartphones, or IoT devices. This paper makes the case for arbitrary quantization as a compelling approximation technique that exposes quality vs. energy tradeoffs and provides practical error guarantees. We present QAPPA (Quality Autotuner for Precision Programmable Accelerators), an autotuning framework for C/C++ programs that automatically minimizes the precision of each arithmetic and memory operation to meet user defined application level quality guarantees. QAPPA integrates energy models of precision scaling mechanisms to produce bandwidth and energy savings estimates for precision scalable accelerator designs. We show that QAPPA can exploit precision scaling mechanisms to meet arbitrary user-provided quality targets on the PERFECT benchmark suite to achieve significant energy savings and memory bandwidth reduction.

关键词： Quantization (signal) Bandwidth Benchmark testing hardware Signal to noise ratio Adders Kernel

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Communication Optimization for Thermal Reliable Many-core systems 12

Work-in-Progress: Communication Optimization for Thermal Rel...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Liu, Weichen Yang, Lei Jiang, Weiwen Guan, Nan Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore Chongqing Univ Coll Comp Sci Chongqing Peoples R China Hong Kong Polytech Univ Dept Comp Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781450351850

system-level thermal management techniques normally map applications on non-adjacent cores to guarantee the safe temperature in many-core systems, while the communication efficiency will be oppositely affected by long-distance data transmission over conventional Network-on-Chips (NoC). SMART NoC has enabled single-cycle multi-hop bypass channels between distant cores, which can significantly reduce inter-processor communication latency. However, communication efficiency of SMART will be significantly diminished by express bypass break due to communication conflict. In order to achieve communication optimization with guaranteed system thermal reliability, we propose a dynamic re-configuration method for logical interconnection topology through task mapping on top of SMART NoC. Active cores are physically decentralized on chip for better heat dissipation, while communication overhead can be reduced by minimized communication conflict and maximized bypass routing. Applicability and effectiveness of the proposed technique can be improved with significant achievements in reducing communication overhead and improving application performance, compared with state-of-the-art techniques.

关键词： Reliability Silicon Schedules Topology Optimization system-on-chip

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：