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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 853 条记录，以下是231-240 订阅

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Runtime requirements monitoring for state-based hardware: work-in-progress 18

Runtime requirements monitoring for state-based hardware: wo...

引用

Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Minjun Seo Roman Lysecky University of Arizona

ISBN: (纸本)9781538655627

This paper presents a requirements-driven methodology enabling efficient runtime monitoring of hardware in embedded systems. We present a novel method for extracting hardware verification requirements from state-based hardware models to construct a hierarchical runtime monitoring graph (HRMG) that can be efficiently used at runtime to verify correctness.

关键词： runtime requirements verification formal verification models hardware verification non-intrusive monitoring

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hardware implementation of a multi-mode-aware mixed-criticality scheduler: work-in-progress 18

Hardware implementation of a multi-mode-aware mixed-critical...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Sena Hounsinou Aishwarya Vasu Harini Ramaprasad Southern Illinois University University of North Carolina

ISBN: (纸本)9781538655627

To minimize size, weight, power, and cost, the industry aims at consolidating different criticality applications on the same hardware platform. In such a mixed-criticality environment, it is challenging to contain the overhead due to potential mode changes under overload conditions. Traditional scheduler implementation at the software level introduces additional overheads due to timer interrupt processing and context switching. To minimize overall software overhead and to improve timing predictability, in this paper, we propose an implementation of the mixed-criticality scheduler in the hardware that is capable of detecting task-overruns and making mode transitions seamlessly.

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AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress 18

AMVP - a high performance virtual platform using parallel sy...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Jan Henrik Weinstock Róbert Lajos Bücs Florian Walbroel Rainer Leupers Gerd Ascheid RWTH Aachen University

ISBN: (纸本)9781538655627

This paper presents AMVP - a systemC based simulator for ARM multicore platforms designed as a tool for early SW development during platform bring-up. It uses a parallel systemC simulation approach to counter the performance slowdown incurred when simulating multi-processor designs. AMVP is sufficiently detailed to support running and debugging unmodified SW images of popular benchmark applications and modern OS kernels like Linux.

关键词： parallel systemC simulation parallel discrete event simulation electronic system level

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A chip-level security framework for assessing sensor data integrity: work-in-progress 18

A chip-level security framework for assessing sensor data in...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Taimour Wehbe Vincent J. Mooney David C. Keezer Georgia Institute of Technology

ISBN: (纸本)9781538655627

The continuously increasing inter-connectivity of sensor nodes that form the basis of the Internet-of-Things results in new avenues of attack exploitable by adversaries to maliciously modify data captured by these nodes. In this work, we present a framework for detecting malicious hardware alterations that attempt to attack state-of-the-art microchips that form these sensor nodes. Specifically, we focus on extremely small hardware Trojans (HTs) that attempt to modify sensor data right away as the data is received on a state-of-the-art chip fabricated in an untrusted facility. We present a dual-chip approach composed of an untrusted state-of-the-art prover chip and a trusted verifier chip, where the verifier continuously challenges the prover at run-time to ensure correct operation and assess the integrity of the captured data. Our preliminary analysis of the proposed mechanism shows that HT attacks anywhere on the untrusted state-of-the-art chip are detected and flagged preventing maliciously altered data to be transmitted out of the sensor node.

关键词： embedded systems security hardware trojans malicious design modifications sensor networks data integrity security in hardware hardware attacks and countermeasures

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On leveraging approximations for exact system-level design space exploration: work-in-progress 18

On leveraging approximations for exact system-level design s...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Kai Neubauer Christian Haubelt Philipp Wanko Torsten Schaub University of Rostock Germany University of Potsdam Germany

ISBN: (纸本)9781538655627

In order to find good design points for embedded systems, an efficient exploration of the design space is imperative. The ever-increasing complexity of embedded systems, however, results in a deterioration of the overall exploration performance. The DSE essentially consists of two parts: (1) the search for feasible solutions and (2) the evaluation of found feasible solutions. While the search has been massively improved by ASPmT-based strategies, the evaluation emerges as the main bottleneck. Tragically, evaluating bad solutions takes as much time as evaluating good ones. Hence, in this paper we study the utilization of approximations in the evaluation process integrated in an ASPmT-based DSE to identify bad solutions more quickly while still retaining the exact Pareto-front.

关键词： system-level design approximation design space exploration

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2014 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2014

2014 International Conference on Hardware/Software Codesign ...

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2014 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2014

ISBN: (纸本)9781450330510

The proceedings contain 35 papers. The topics discussed include: HEFT: a hybrid system-level framework for enabling energy-efficient fault-tolerance in NoC based MPSoCs;an efficient technique for computing importance measures in automatic design of dependable embedded systems;towards scalable symbolic routing for multi-objective networked embedded system design and optimization;hardware/software co-design for a wireless sensor network platform;a PCM translation layer for integrated memory and storage management;leveraging microarchitectural side channel information to efficiently enhance program control flow integrity;saving energy without defying deadlines on mobile GPU-based heterogeneous systems;prediction and control of bursty cloud workloads: a fractal framework;TSP: thermal safe power - efficient power budgeting for many-core systems in dark silicon;and flattening-based mapping of imperfect loop nests for CGRA.

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HW/SW Co-design Experimental Framework using Configurable SoCs

HW/SW Co-design Experimental Framework using Configurable So...

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international conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Xu, Siyuan Chen, Jianqi Schafer, Benjamin Carrion Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75083 USA

ISBN: (纸本)9781538637975

This paper presents an open source HW/SW co-design experimental platform based on behavioral benchmarks mapped onto a programmable SoC using High-Level synthesis. HW/SW co-design has become extremely relevant in today's VLSI design processes. Due to the unstoppable increase in transistor count of integrated circuits (ICs), most ICs are currently heterogenous SoCs containing micro-processors, memories, interfaces and dedicated hardware accelerators. This has lead FPGA vendors to introduce programmable/configurable SoCs (CSoC), e.g. Altera's Cyclone/Arria/Stratix SoCs and Xilinx's Zynq family. At the same time, newer design methodologies are required to increase the design productivity like HLS. The main problem is that there are no benchmarks that can be directly mapped onto these CSoC using HLS to conduct research in HW/SW co-design as well as to teach HW/SW co-design. A HW/SW co-design experimental framework is presented here to bridge this gap. A set of synthesizable systemC designs have been created and ported onto a Cyclone V SoC FPGA. The designs have been created in such a way that they can be fully executed on the embedded processor or accelerated by mapping the most computationally intensive kernel onto the reconfigurable fabric. A software layer allows the creation of different HW/SW configurations by allowing tasks to be executed on the embedded processor or mapped as hardware accelerator on the reconfigurable logic. The complete environment is open source and available online. A running time and energy comparison between the benchmarks mapped onto a desktop PC processor in ANSI-C and systemC, an embedded ARM processor and the ARM+FPGA version are presented showing that the accelerated benchmarks do only lead to speed-ups compared to the embedded processor's version when the system's communication part (sending and receiving data) is lower than 50% of the total runtime. We believe that this open source HW/SW design platform is a good starting point to enco

关键词： embedded systems field programmable gate arrays hardware-software codesign system-on-chip VLSI Field programmable gate arrays Co-design hardware/software co-design system-on-chip Very large scale integration Embedded systems hue lightness saturation embedded processor hardware accelerator BENCHMARKS SYNTHETIC ORGANIC CHEMICALS open source

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FPGA-Accelerated for Constrained High Dispersal Network 15

FPGA-Accelerated for Constrained High Dispersal Network

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15th IEEE international Symposium on Parallel and Distributed Processing with Applications (ISPA) / 16th IEEE international conference on Ubiquitous Computing and Communications (IUCC)

作者： Chen, Yanliang Zhu, Minghua Xiao, Bo Meng, Dan East China Normal Univ MOE Res Ctr Software Hardware Codesign Engn & App Shanghai Peoples R China

ISBN: (纸本)9781538637906

In recent years, the Deep Neural Network (DNN) has been successfully used in image classification. Most of existing DNN often need to learn a very large set of parameters, which require a huge amount of computational resources and time to train these model parameters using the gradient descent and back-propagation procedure. To solve this issue, the PCANet has been developed for high efficient design and training of the DNN. Compared with traditional DNN, PCANet has simpler structure and better performance, which makes it attractive for hardware design. To overcome the limitations of PCANet and significantly improve its performance, we have proposed a novel model named Constrained High Dispersal Network (CHDNet) which is a variant of PCANet. In this paper, we implement the CHDNet on the Xilinx ZYNQ FPGA to ensure the instantaneity of the system with lower power than personal computer needed by taking advantage of the algorithmic parallelism and ZYNQ architecture. Our experimental results over two major datasets, the MNIST dataset for handwritten digits recognition, and the Extended Yale B dataset for face recognition, demonstrate that our model of implementation on FPGA is more than 15x faster than software implementation on PC (Intel i7-4720HQ, 2.6GHz).

关键词： Image classification Deep neural network FPGA High-level synthesis

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Efficient virtual memory sharing via on-accelerator page table walking in heterogeneous embedded SoCs

Efficient virtual memory sharing via on-accelerator page tab...

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ACM Transactions on Embedded Computing systems

作者： Vogel, Pirmin Kurth, Andreas Weinbuch, Johannes Marongiu, Andrea Benini, Luca Integrated Systems Laboratory ETH Zurich Gloriastrasse 35 Zurich8092 Switzerland Electrical Electronic and Information Engineering Department University of Bologna Viale Risorgimento 2 Bologna40126 Italy

Shared virtual memory is key in heterogeneous systems on chip (SoCs) that combine a general-purpose host processor with a many-core accelerator, both for programmability and performance. In contrast to the fullblown, hardware-only solutions predominant in modern high-end systems, lightweight hardware-software co-designs are better suited in the context of more power- and area-constrained embedded systems and provide additional benefits in terms of flexibility and predictability. As a downside, the latter solutions require the host to handle in software synchronization in case of page misses as well as miss handling. This may incur considerable run-time overheads. In this work, we present a novel hardware-software virtual memory management approach for many-core accelerators in heterogeneous embedded SoCs. It exploits an accelerator-side helper thread concept that enables the accelerator tomanage its virtualmemory hardware autonomously while operating cache-coherently on the page tables of the user-space processes of the host. This greatly reduces overhead with respect to host-side solutions while retaining flexibility. We have validated the design with a set of parameterizable benchmarks and real-world applications covering various application domains. For purely memory-bound kernels, the accelerator performance improves by a factor of 3.8 compared with host-based management and lies within 50% of a lower-bound ideal memory management unit. © 2017 ACM.

关键词： Memory management units Acceleration Benchmarking Computer operating systems Embedded systems hardware hardware software codesign Linux Physical addresses system on chip Heterogeneous systems High end systems Many core accelerators Novel hardware Programmability Shared virtual memory Virtual memory Virtual memory management

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Optimal Functional-Unit Assignment and Buffer Placement for Probabilistic Pipelines 16

Optimal Functional-Unit Assignment and Buffer Placement for ...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Jiang, Weiwen Sha, Edwin H. -M. Zhuge, Qingfeng Chen, Xianzhang Chongqing Univ Coll Comp Sci Chongqing Peoples R China

ISBN: (纸本)9781450344838

Applications, such as streaming applications, modeled by task graphs can be efficiently executed in a pipelined fashion. In synthesizing application-specific heterogeneous pipelined systems, where to place buffers (called buffer placement) and what type of functional units to execute each task (called functional assignment) are two critical problems. In reality, the execution time of each task may not be fixed, which makes the above two problems much more challenging. In this paper, we model the execution time of each task on different types of functional units as a random variable. Our objective is to obtain the optimal functional assignment and buffer placement, such that the resultant pipeline can satisfy the timing requirement with the minimum cost under the guaranteed confidence probability. This paper presents efficient algorithms to achieve the objective. Experiments show that other techniques cannot find any feasible solutions in many cases while ours can. Even for the cases where they can find feasible solutions, our algorithms achieve the minimum cost which gives a significant reduction on the total cost, compared with existing techniques.

关键词： High-level synthesis application-specific system optimal algorithms probabilistic scenario

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