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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

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A design to reduce write amplification in object-based NAND flash devices

A design to reduce write amplification in object-based NAND ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jie Guo Chuhan Min Tao Cai Yiran Chen Department of Electrical and Computer Engineering University of Pittsburgh School of Computer Science and Telecommunication Engineering Jiangsu University

ISBN: (纸本)9781509035908

Write amplification is a major cause of performance and endurance degradations in NAND flash based storage systems. In an object-based NAND flash device, two causes of write amplification are onode partial update and cascading update. Updating one onode, a kind of small-sized object metadata, invokes partial page update (i.e., onode partial update) that incurs unnecessary migration of the un-updated data. An cascading update denotes that object metadata is updated in a cascading manner due to erase-before-program property of NAND flash memory. In this work, we propose a system design to alleviate onode partial update and cascading update. The proposed system design includes: 1) A multi-level garbage collection technique to minimize unnecessary data migration incurred by onode partial update; 2) A B+ table tree and selective cache design to reduce the write operations associated with cascading update; and 3) A power failure handling technique to guarantee system consistency. Experiment results show that our proposed design can achieve up to 20% write reduction compared to the best state-of-the-art.

关键词： Metadata Indexes system analysis and design Memory management Random access memory Resource management

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An accurate and flexible early memory system power evaluation approach using a microcomponent method

An accurate and flexible early memory system power evaluatio...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chi-Kang Chen Hsin-I Wu Chi-Ting Hsiao Ren-Song Tsay Industrial Technology Research Institute Hsinchu Taiwan Department of Computer Science National Tsing-Hua University Hsinchu Taiwan

ISBN: (纸本)9781509035908

As energy efficiency has become a primary concern, system designers have greater need for a flexible and highly accurate power estimation method for evaluating different architecture options. Since memory is an increasingly dominant power consumer, we reexamine existing memory power models and propose a highly efficient microcomponent-based approach with data-aware refinement for accurate system-level power estimations. The key contribution of our approach is that the proposed microcomponent method allows designers to use flexible architecture compositions. Our approach identifies the common microcomponents used by internal memory commands and accurately pre-calibrates the power consumption pattern of each microcomponent. We decompose target design architectures into these microcomponents to easily derive accurate power estimates. To achieve very high accuracy, we consider the data variation effect by leveraging the fact that memory circuit is mainly doing data passing and hence a simple interpolation technique can further boost accuracy. Our experiments show that the proposed approach produces accurate results of less than 2% error rate in average for system power analysis.

关键词： Integrated circuit modeling Random access memory Power demand Memory management Timing Computational modeling Estimation

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A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory

A disturbance-aware sub-block design to improve reliability ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hung-Sheng Chang Yuan-Hao Chang Tei-Wei Kuo Yu-Ming Chang Hsiang-Pang Li Macronix International Co. Ltd. Emerging System Lab. Hsinchu Taiwan R.O.C. Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan R.O.C. lnstitute of Information Science Academia Sinica Taipei Taiwan R.O.C. Research Center for Information Technology Innovation Academia Sinica Taipei Taiwan R.O.C.

ISBN: (纸本)9781509035908

The reliability problem of modern flash-memory chips quickly deteriorates because of the nature of MLC chips. Although the vertical stacking of storage cells in 3D flash-memory chips dramatically increases the bit density, compared to 2D chips, it also results in severe disturbance problems. In this work, we propose to create sub-blocks in the MTD layer by considering different program disturb resistance patterns, without any hardware cost. In particular, a disturbance-aware sub-block design is proposed to utilize the hotness information of data to further improve the reliability of 3D MLC flash memory by smartly choosing sub-blocks to use when extra information is available from the flash translation layer. The proposed design was evaluated by a series of experiments over traces from SNIA. It was shown that the disturb errors could be reduced by at least 50% under DFTL and BL, i.e., a page-level FTL and a block-level FTL design, compared to the conventional MLC programming designs.

关键词： Three-dimensional displays Reliability engineering Resistance Programming Logic gates Error correction codes

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Efficient design space exploration by knowledge transfer

Efficient design space exploration by knowledge transfer

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Dandan Li Senzhang Wang Shuzhen Yao Yu-Hang Liu Yuanqi Cheng Xian-He Sun School of Computer Science and Engineering Beihang University Beijing China College of Computer Science and Technology Nanjing University of Aeronautics and Astronautics Nanjing China Collaborative Innovation Center of Novel Software Technology and Industrialization Nanjing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Illinois Institute of Technology Chicago USA

ISBN: (纸本)9781509035908

Due to the exponentially increasing size of design space of microprocessors and time-consuming simulations, predictive models have been widely employed in design space exploration (DSE). Traditional approaches mostly build a program-specific predictor that needs a large number of program-specific samples. Thus considerable simulation cost is required for each program. In this paper, we study the novel problem of transferring knowledge from the labeled samples of previous programs to help predict the responses of the new target program whose labeled samples are very sparse. Inspired by the recent advances of transfer learning, we propose a transfer learning based DSE framework TrDSE to build a more efficient and effective predictive model for the target program with only a few simulations by borrowing knowledge from previous programs. Specifically, TrDSE includes two phases: 1) clustering the programs based on the proposed orthogonal array sampling and the distribution related features, and 2) with the guidance of clustering results, predicting the responses of configurations in design space of the target program by a transfer learning based regression algorithm. We evaluate the proposed TrDSE on the benchmarks of SPEC CPU 2006 suite. The results demonstrate that the proposed framework is more efficient and effective than state-of-art DSE techniques.

关键词： Predictive models Knowledge transfer Clustering algorithms Feature extraction Prediction algorithms Training data Space exploration

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Keynote talk II: Multiform logical time for Me/Mo-codesign

Keynote talk II: Multiform logical time for Me/Mo-codesign

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Robert de Simone Inria Le Chesnay ÃŽle-de-France FR

ISBN: (纸本)9781509027927

There is now a consistent corpus of models and methods for software/hardware codesign (scope of MeMoCoDe). Still, while success is quite established at both ends of the spectrum (High-Level hardware synthesis, and system Engineering), the adoption of such software modeling approach inside mainstream software Engineering communities could easily be improved. This is certainly so because some of the principles of application modeling do not exactly match, or elsewhere do not focus upon the same concerns, as traditional coding style. Putting forth the relevant important concepts for application modeling, while investigating their relevance to traditional engineering experience, is certainly a way to counter confusion. We view the notion of Multiform Logical Time as such a fundamental concept. In a first part of the talk we consider the premises of Multiform Logical Time in Embedded Design (its origin, its relevance at places of design flows); in a second part we introduce a small declarative language to express logical time properties, study its expressiveness and its associated analysis techniques.

关键词： Unified modeling language Embedded systems Semantics Parallel processing Algebra Model checking Collaboration

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Human-machine communication for assistive IoT technologies

Human-machine communication for assistive IoT technologies

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Alexandra Porter Md Muztoba Umit Y. Ogras School of Electrical Computer and Energy Engineering Arizona State University

ISBN: (纸本)9781509035908

Despite the phenomenal advances in the computational power and functionality of electronic systems, human-machine interaction has largely been limited to simple control panels, keyboard, mouse and display. Consequently, these systems either rely critically on close human guidance or operate almost independently from the user. An exemplar technology integrated tightly into our lives is the smartphone. However, the term “smart” is a misnomer, since it has fundamentally no intelligence to understand its user. The users still have to type, touch or speak (to some extent) to express their intentions in a form accessible to the phone. Hence, intelligent decision making is still almost entirely a human task. A life-changing experience can be achieved by transforming machines from passive tools to agents capable of understanding human physiology and what their user wants [1]. This can advance human capabilities in unimagined ways by building a symbiotic relationship to solve real world problems cooperatively. One of the high-impact application areas of this approach is assistive internet of things (IoT) technologies for physically challenged individuals. The Annual World Report on Disability reveals that 15% of the world population lives with disability, while 110 to 190 million of these people have difficulty in functioning [1]. Quality of life for this population can improve significantly if we can provide accessibility to smart devices, which provide sensory inputs and assist with everyday tasks. This work demonstrates that smart IoT devices open up the possibility to alleviate the burden on the user by equipping everyday objects, such as a wheelchair, with decision-making capabilities. Moving part of the intelligent decision making to smart IoT objects requires a robust mechanism for human-machine communication (HMC). To address this challenge, we present examples of multimodal HMC mechanisms, where the modalities are electroencephalogram (EEG), speech commands, and mot

关键词： virtualisation control engineering computing decision making electroencephalography human-robot interaction Internet of Things medical computing medical robotics smart phones Virtualization control engineering computing Internet of things Smartphone Human machine interaction medical computing medical robotics Electroencephalography Intelligent decision making decision making hardware motion compensation world population disability

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Multiform logical time for me/mo-codesign 16

Multiform logical time for me/mo-codesign

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Proceedings of the 14th ACM-IEEE international conference on Formal Methods and Models for system Design

作者： Robert de Simone INRIA France

ISBN: (纸本)9781509027910

There is now a consistent corpus of models and methods for software/hardware codesign (scope of MeMoCoDe). Still, while success is quite established at both ends of the spectrum (High-Level hardware synthesis, and system Engineering), the adoption of such software modeling approach inside mainstream software Engineering communities could easily be improved. This is certainly so because some of the principles of application modeling do not exactly match, or elsewhere do not focus upon the same concerns, as traditional coding style. Putting forth the relevant important concepts for application modeling, while investigating their relevance to traditional engineering experience, is certainly a way to counter confusion. We view the notion of Multiform Logical Time as such a fundamental *** a first part of the talk we consider the premises of Multiform Logical Time in Embedded Design (its origin, its relevance at places of design flows); in a second part we introduce a small declarative language to express logical time properties, study its expressiveness and its associated analysis techniques.

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hardware synthesis from a Recursive Functional Language

Hardware Synthesis from a Recursive Functional Language

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Zhai, Kuangya Townsend, Richard Lairmore, Lianne Kim, Martha A. Edwards, Stephen A. Columbia Univ New York NY 10027 USA

ISBN: (纸本)9781467383219

An Abstraction in hardware description languages stalled at the register-transfer level decades ago, yet few alternatives have had much success, in part because they provide only modest gains in expressivity. We propose to make a much larger jump: a compiler that synthesizes hardware from behavioral functional specifications. Our compiler translates general Haskell programs into a restricted intermediate representation before applying a series of semantics-preserving transformations, concluding with a simple syntax-directed translation to systemVerilog. Here, we present the overall framework for this compiler, focusing on the intermediate representations involved and our method for translating general recursive functions into equivalent hardware. We conclude with experimental results that depict the performance and resource usage of the circuitry generated with our compiler.

关键词： Functional hardware Recursion High-Level synthesis

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A parallelizable approach for mining likely invariants

A parallelizable approach for mining likely invariants

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Danese, Alessandro Piccolboni, Luca Pravadelli, Graziano Univ Verona Str Grazie 15 I-37134 Verona Italy

ISBN: (纸本)9781467383219

A relevant aspect in design analysis and verification is monitoring how logic relations among different variables change at run time. Current static approaches suffer from scalability problems that prevent their adoption on large designs. On the contrary, dynamic techniques scale better from the memory-consumption point of view. However, to achieve a high accuracy, they require to analyse a huge number of ( long) execution traces, which results in time-consuming phases. In this paper, we present a new efficient approach to automatically infer logic relations among the variables of a design implementation. Both a sequential and a GPU-oriented parallel implementation are proposed to dynamically extract likely invariants from execution traces on different time windows. Execution traces composed of millions of simulation instants can be efficiently analysed.

关键词： data mining graphics processing units hardware-software codesign GPU-oriented parallel implementation design analysis design verification dynamic techniques execution traces likely invariants mining logic relations memory-consumption view point parallelizable approach scalability problems sequential parallel implementation static approaches time windows time-consuming phases Accuracy Analytical models Computer architecture Engines Graphics processing units Instruction sets Instruments design analysis instruction sets design verification Time windows hardware/software co-design Computer Architecture Graphics Processing Unit Engines ANALYSIS MODELS data mining Legal Executions time phase Invariant

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The Shift to Multicores in Real-Time and Safety-Critical systems

The Shift to Multicores in Real-Time and Safety-Critical Sys...

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Saidi, Selina Ernst, Rolf Uhrig, Sascha Theiling, Henrik de Dinechin, Benoit Dupont Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Airbus Grp Innovat Leiden Netherlands SYSGO AG Mainz Germany Kalray SA Montbonnot St Martin France

ISBN: (纸本)9781467383219

In real-time and safety-critical systems, the move towards multicores is becoming unavoidable in order to keep pace with the increasing required processing power and to meet the high integration trend while maintaining a reasonable power consumption. However, standard multicore systems are mainly designed to increase average performance, whereas embedded systems have additional requirements with respect to safety, reliability and realtime behavior. Therefore, the shift to multicores raises several challenges the embedded community has to face. These challenges involve the design of certifiable multicore platforms, the management of shared resources and the development/integration of parallel software. These issues are encountered at different steps of system development, from modeling and design to software implementation and hardware deployment. Therefore, both multicore/semiconductor manufacturers and the real-time community have to bridge the gap in order to meet the challenges imposed by multicores. The goal of this paper is to trigger such a discussion as an attempt to bridge the gap between the two worlds and to raise awareness about the hurdles and challenges that need to be tackled.

关键词： embedded systems parallel processing power aware computing resource allocation safety-critical software certifiable multicore platform design hardware deployment multicore systems parallel software development parallel software integration real-time system safety-critical system shared resource management software implementation system development Aerospace electronics hardware Multicore processing Real-time systems Safety software Timing safety-critical software real-time systems Embedded systems power aware computing software implementation avionics systems development computer software management of resources Computer hardware PARALLEL PROCESSING (COMPUTERS) Resource utilization Consumer safety safety software design

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