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HSAemu - A Full system Emulator for HSA Platforms 14

HSAemu - A Full System Emulator for HSA Platforms

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Ding, Jiun-Hung Hsu, Wei-Chung Jeng, Bai-Cheng Hung, Shih-Hao Chung, Yeh-Ching Natl Tsing Hua Univ Hsinchu 30013 Taiwan Natl Taiwan Univ Taipei 10617 Taiwan

ISBN: (纸本)9781450330510

Heterogeneous system Architecture (HSA) is an open industry standard designed to support a large variety of data-parallel and task-parallel programming models. Currently, most of HSA hardware and software components are still in development. It is helpful to provide various heterogeneous simulation environments for HSA developers in developing HSA software stacks. This paper presents the design of HSAemu, a full system emulator for the HSA platform, and illustrates how those HSA features are implemented in the simulator. HSAemu provides an infrastructure of heterogeneous simulation environments by supporting required HSA features, including hUMA, hQ and HSAIL. Based on the infrastructure, HSAemu provide two simulation models, FastSim and DeepSim, for high-speed functional emulation and slow cycle-accurate simulation, respectively. In our preliminary experiments, HSAemu helps test a complete HSA software stack and profile system performance. Our case studies show that HSAemu is very useful as a hardware/software co-design tool for heterogeneous systems.

关键词： HSA GPU simulation parallel simulation

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On-Chip Self-Awareness Using Cyberphysical-systems-On-Chip (CPSoC) 14

On-Chip Self-Awareness Using Cyberphysical-Systems-On-Chip (...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Sarma, S. Dutt, N. Gupta, P. Nicolau, A. Venkatasubramanian, N. Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90024 USA

ISBN: (纸本)9781450330510

We presented CPSoC, a self-aware sensor-actuator-rich MPSoC platform that deploys the computation-communication-control codesign of CPS together with cross-layer adaptations to achieve multiple design objectives. The CPSoC paradigm enables on-chip self-awareness (selective or opportunistic) adaptation using the concepts of cross-layer physical and virtual sensing and actuations. In [3] we illustrate CPSoC's potential for self-awareness and cross-layer adaptations using several examples and have developed an FPGA prototype to emulate a typical CPSoC.

关键词： actuators field programmable gate arrays sensors system-on-chip CPSoC paradigm FPGA prototype control-communication-computing system codesign cyberphysical-system-on-chip on-chip cross-layer actuation on-chip cross-layer sensing on-chip self-awareness on-chip sensing physical environment sensor-actuator rich many-core computing platforms Aging Computer architecture Delays Predictive models Quality of service Sensors system-on-chip system-on-chip Field programmable gate arrays Sensors Computer Architecture Quality of service physical environment Prediction models self-awareness actuators Aging Awareness delay

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hardware/software Co-design for A Wireless Sensor Network Platform 14

Hardware/Software Co-design for A Wireless Sensor Network Pl...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Hsieh, Chih-Ming Samie, Farzad Srouji, M. Sammer Wang, Manyi Wang, Zhonglei Henkel, Joerg KIT CES Karlsruhe Germany

ISBN: (纸本)9781450330510

Wireless sensor networks have become shared resources providing sensing services to monitor ambient environment. The tasks performed by the sensor nodes and the network structure are becoming more and more complex so that they cannot be handled efficiently by traditional sensor nodes any more. The traditional sensor node architecture, which has software implementation running on a fixed hardware design, is no longer fit to the changing requirements when new applications with complex computation are added to this shared infrastructure due to several reasons. First, the operation behavior changes because of the application requirements and the environmental conditions which makes a fixed architecture not efficient all the time. Second, to collaborate with other already deployed sensor networks and to maintain an efficient network structure, the sensor nodes require flexible communication capabilities. Furthermore, the information required to determine an efficient hardware/software co-design under the system constraints cannot be known a priori. Therefore a platform which can adapt to run-time situations will play an important role in wireless sensor networks. In this paper, we present a hardware/software co-design framework for a wireless sensor platform, which can adaptively change its hardware/software configuration to accelerate complex operations and provides a flexible communication mechanism to deal with complex network structures. We perform real-world measurements on our prototype to analyze its capabilities. In addition, our case studies with prototype implementation and network simulations show the energy savings of the sensor network application by using the proposed design with run-time adaptivity.

关键词： reconfiguration sensor networks hardware accelerator FPGA low power multi-radio

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HEFT: A Hybrid system-Level Framework for Enabling Energy-Efficient Fault-Tolerance in NoC based MPSoCs 14

HEFT: A Hybrid System-Level Framework for Enabling Energy-Ef...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Zou, Yong Pasricha, Sudeep Colorado State Univ Dept Elect & Comp Engn Ft Collins CO 80523 USA

ISBN: (纸本)9781450330510

In emerging CMOS process technologies, network-on-chip (NoC) fabrics are increasingly becoming susceptible to transient faults. Fault-tolerance mechanisms that are typically employed in NoCs usually entail significant energy overheads that are expected to become prohibitive as fault rates increase in future CMOS technologies. We propose a system-level framework called HEFT to trade-off energy consumption and fault-tolerance in the NoC fabric. Our hybrid framework tackles the challenge of enabling energy-efficient resilience in NoCs in two phases: at design time and at runtime. At design time, we implement an algorithm to guide the robust mapping of cores on to a die while satisfying application bandwidth and latency constraints. At runtime we devise a prediction algorithm to monitor and detect changes in fault susceptibility of NoC components, to intelligently balance energy consumption and reliability. Experimental results show that HEFT improves energy/reliability ratio of synthesized solutions by 8-20%, while meeting application performance goals, when compared to multiple prior works on reliable system-level NoC design.

关键词： system-level design networks-on-chip fault-tolerance

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Code Generation from a Domain-specific Language for C-based HLS of hardware Accelerators 14

Code Generation from a Domain-specific Language for C-based ...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Reiche, Oliver Schmid, Moritz Hannig, Frank Membarth, Richard Teich, Juergen Friedrich Alexander Univ Erlangen NUrnberg FAU Dept Comp Sci Erlangen Germany Saarland Univ Intel Visual Comp Inst Saarbrucken Germany

ISBN: (纸本)9781450330510

As today's computer architectures are becoming more and more heterogeneous, a plethora of options including CPUs, GPUs, DSPs, reconfigurable logic (FPGAs), and other application-specific processors come into consideration for close-to-sensor processing. Especially, in the domain of image processing on mobile devices, among numerous design challenges, a very stringent energy budget is of utmost importance, making embedded GPUs and FPGAs ideal targets for implementation. Recently, the HIPA(cc) framework was proposed as a means for automatic code generation of image processing algorithms for embedded GPUs, based on a Domain-Specific Language (DSL). Despite of huge advancements in High-Level synthesis (HLS) for FPGAs, designers are still required to have detailed knowledge about coding techniques and the targeted architecture to achieve efficient solutions. As a remedy, in this work, we propose code generation techniques for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, numerous high-level transformations, and automatic test bench generation. We evaluate our approach by comparing the resulting hardware accelerators to existing frameworks in terms of performance and resource requirements. Moreover, we assess the achieved energy efficiency in contrast to software implementations, generated by HIPAcc from the same code base, executed on GPUs.

关键词： Code generation domain specific language image processing high-level synthesis hardware accelerator FPCA CPU

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Cost-Effective Design of a Hybrid Electrical Energy Storage system for Electric Vehicles 14

Cost-Effective Design of a Hybrid Electrical Energy Storage ...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Zhu, Di Yue, Siyu Park, Sangyoung Wang, Yanzhi Chang, Naehyuck Pedram, Massoud Univ Southern Calif Los Angeles CA 90089 USA Seoul Natl Univ Seoul South Korea Korea Adv Inst Sci & Technol Daejeon South Korea

ISBN: (纸本)9781450330510

A comprehensive economic feasibility analysis and a cost-driven design methodology are essential to the successful application of hybrid electrical energy storage (BEES) systems in electric vehicles (EVs). This paper thus focuses on designing a cost-effective and high-performance BEES system for EVs, comprising of a supercapacitor bank and a lithium-ion (Li-ion) battery bank. In particular, the paper formulates the capacity provisioning problem for the EV BEES system so as to minimize the total system cost, utilizing accurate models of the battery cycle efficiency and state of health, characteristics of the supercapacitor bank, and dynamics of the EV. The aforesaid problem is subsequently solved by combining a gradient descent-based approach with a simulated annealing-based algorithm. Simulation results show that the proposed EV BEES system achieves 21% lower total cost per day and 30% higher fuel economy compared to a baseline homogeneous electrical energy storage system comprised of Li-ion batteries only.

关键词： Electric vehicles hybrid energy storage systems cost efficiency

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system-level memory optimization for high-level synthesis of component-based SoCs 14

System-level memory optimization for high-level synthesis of...

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2014 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2014

作者： Pilato, Christian Mantovani, Paolo Di Guglielmo, Giuseppe Carloni, Luca P. Department of Computer Science Columbia University New YorkNY United States

ISBN: (纸本)9781450330510

The design of specialized accelerators is essential to the success of many modern systems-on-Chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and optimization of an accelerator. Still, these methodologies and tools offer only limited support for the optimization of the memory structures, which are often responsible for most of the area occupied by an accelerator. To address these limitations, we present a novel methodology to automatically derive the memory subsystems of SoC accelerators. Our approach enables compositional design-space exploration and promotes design reuse of the accelerator specifications. We illustrate its effective-ness by presenting experimental results on the design of two accelerators for a high-performance embedded application. Copyright 2014 ACM.

关键词： system-on-chip

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system-of-PUFs: Multilevel Security for Embedded systems 14

System-of-PUFs: Multilevel Security for Embedded Systems

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Konigsmark, S. T. Choden Hwang, Leslie K. Chen, Deming Wong, Martin D. F. Univ Illinois Dept Elect & Comp Engn Champaign IL 61820 USA

ISBN: (纸本)9781450330510

Embedded systems continue to provide the core for a wide range of applications, from smart-cards for mobile payment to smart-meters for power-grids. The resource and power dependency of embedded systems continues to be a challenge for state-of-the-art security practices. Moreover, even theoretically secure algorithms are often vulnerable in their implementation. With decreasing cost and complexity, physical attacks are an increasingly important threat. This threat led to the development of Physically Unclonable Functions (PUFs) which are disordered physical systems with various applications in hardware security. However, consistent security oriented design of embedded systems remains a challenge, as most formalizations and security models are concerned with isolated physical components or high-level concept. We provide four unique contributions: (i) We propose a system-level security model to overcome the chasm between secure components and requirements of high-level protocols;this enables synergy between component-oriented security formalizations and theoretically proven protocols. (ii) An analysis of current practices in PUF protocols using the proposed system-level security model;we identify significant issues and expose assumptions that require costly security techniques. (iii) A system-of-PUF (SoP) that utilizes the large PUF design-space to achieve security requirements with minimal resource utilization;SoP requires 64% less gate-equivalent units than recently published schemes. (iv) A multilevel authentication protocol based on SoP which is validated using our system-level security model and which overcomes current vulnerabilities. Furthermore, this protocol offers breach recognition and recovery.

关键词： Physically Unclonable Functions hardware Authentication

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Metronomy: A Function-Architecture Co-simulation Framework for Timing Verification of Cyber-Physical systems 14

Metronomy: A Function-Architecture Co-simulation Framework f...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Guo, Liangpeng Zhu, Qi Nuzzo, Pierluigi Passerone, Roberto Sangiovanni-Vincentelli, Alberto Lee, Edward A. Univ Calif Berkeley Berkeley CA 94720 USA Univ Calif Riverside Riverside CA 92521 USA Univ Trento Trento TN Italy

ISBN: (纸本)9781450330510

As the design complexity of cyber-physical systems continues to grow, modeling the system at higher abstraction levels with formal models of computation is increasingly appealing since it enables early design verification and analysis. One of the most important aspects in system modeling and analysis is timing. However, it is very challenging to analyze and verify timing at the early design stages, as the design representation is quite abstract and trade-offs have to be made between the performance requirements defined in terms of system functionality and the cost of the feasible architecture that can implement the functionality. In this paper, we present Metronomy, a function-architecture co-simulation framework that integrates functional modeling from Ptolemy and architectural modeling from the Metroll environment via a mapping interface. Metronomy exploits contract theory for timing verification and design space exploration via co-simulation. Two case studies on an electrical power system and a paper-feed sub-system for a high speed printing press demonstrate the effectiveness of our approach.

关键词： Cyber-Physical system Co-simulation Timing

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Dark Silicon as a Challenge for hardware/software Co-Design

Dark Silicon as a Challenge for Hardware/Software Co-Design

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Shafique, Muhammad Garg, Siddharth Mitra, Tulika Parameswaran, Sri Henkel, Joerg Karlsruhe Inst Technol CES Karlsruhe Germany Univ Waterloo Dept ECE Waterloo ON Canada Natl Univ Singapore Sch Comp Singapore Singapore Univ New South Wales Sch Comp Sci & Engn Sydney NSW Australia

ISBN: (纸本)9781450330510

Dark Silicon refers to the observation that in future technology nodes, it may only be possible to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache blocks and so on) in order to stay within the power budget and safe thermal limits, while the other resources will have to be kept powered-off or "dark". In other words, chips will have an abundance of transistors, i.e., more than the number that can be simultaneously powered-on. Heterogeneous computing has been proposed as one way to effectively leverage this abundance of transistors in order to increase performance, energy efficiency and even reliability within power and thermal constraints. However, several critical challenges remain to be addressed including design, automated synthesis, design space exploration and run-time management of heterogeneous dark silicon processors. The hardware/software co-design and synthesis community has potentially much to contribute in solving these new challenges introduced by dark silicon and, in particular, heterogeneous computing. In this paper, we identify and highlight some of these critical challenges, and outline some of our early research efforts in addressing them.

关键词： hardware-software codesign power aware computing automated synthesis design space exploration energy efficiency improvement hardware-software co-design heterogeneous computing heterogeneous dark silicon processors on-chip resources performance improvement power budget power constraint reliability improvement run-time management safe thermal limits thermal constraint transistors Computer architecture hardware Program processors Reliability Silicon Switches hardware/software co-design power budget power aware computing Transistor Device Component Program processors Computer Architecture Silicon Switches performance boost Computer hardware Co-design Space Exploration

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