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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 854 条记录，以下是341-350 订阅

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Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems 13

Bio-inspired ultra lower-power neuromorphic computing engine...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Beiye Liu Miao Hu Hai Li Yiran Chen Chun Xue Electrical & Computer Engineering Department University of Pittsburgh Pittsburgh USA Department of Computer Science City University of Hong Kong Hong Kong China

ISBN: (纸本)9781479914173

Neuromorphic computing, which is inspired by the working mechanism of human brain, recently emerges as a hot research area to combat the contradiction between the limited functions of computing systems and the ever increasing variety of applications. In this work, we will introduce our research on a bio-inspired neuromorphic embedded computing engine named Centaur, which aims to achieve an ultra-high power efficiency beyond One-TeraFlops-Per-Watt by adopting the bio-inspired computation model and the advanced memristor technology. The success of Centaur design may promote the embedded system power efficiency three orders of magnitude from the current level while the small footprint and real-time re-configurability of the design allow an easy integration into MPSoCs, enabling many emerging mobile and embedded applications.

关键词： Neuromorphics Memristors Engines Embedded systems hardware Training Computational efficiency

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A DRAM-flash index for native flash file systems 13

A DRAM-flash index for native flash file systems

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chien-Chung Ho Po-Chun Huang Yuan-Hao Chang Tei-Wei Kuo Department of Computer Science and Information Engineering National Taiwan University Academia Sinica Institute of Information Science College of Information and Communication Engineering Sungkyunkwan University

ISBN: (纸本)9781479914173

Index structures are widely used in file systems and database applications for efficient data management. This paper exploits the respective characteristics of DRAM and flash memory for tree index designs, for which a native file system is taken as an example target in the research. Different from DRAM caching or buffering of flash-memory access in the past work, a hybrid index design that resides over DRAM and flash memory simulaneously is proposed to improve system performance and space management. Tree nodes migrate between DRAM and flash memory, as needed, in response to user access pattern so as to optimize the performance and to reduce managing overhead. The capability of the proposed design is evaluated by a series of experiments, for which we have very encouraging results.

关键词： flash memory index structure native flash file system overflow tree

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synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters 13

Synthesis-friendly techniques for tightly-coupled integratio...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Francesco Conti Andrea Marongiu Luca Benini DEI - Università di Bologna

ISBN: (纸本)9781479914173

Several many-core designs tackle scalability issues by leveraging tightly-coupled clusters as building blocks, where low-latency, high-bandwidth interconnection between a small/medium number of cores and L1 memory achieves high performance/watt. Tight coupling of hardware accelerators into these multicore clusters constitutes a promising approach to further improve performance/area/watt. However, accelerators are often clocked at a lower frequency than processor clusters for energy efficiency reasons. In this paper, we propose a technique to integrate shared-memory accelerators within the tightly-coupled clusters of the STMicroelectronics STHORM architecture. Our methodology significantly relaxes timing constraints for tightly-coupled accelerators, while optimizing data bandwidth. In addition, our technique allows to operate the accelerator at an integer submultiple of the cluster frequency. Experimental results show that the proposed approach allows to recover up to 84% of the slow-down implied by reduced accelerator speed.

关键词： hardware Computer architecture Registers Clocks Ports (Computers) Couplings Bandwidth

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Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor 13

Embedded supercomputing in FPGAs with the VectorBlox MXP Mat...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Aaron Severance Guy G.F. Lemieux VectorBlox Computing Inc. University of British Columbia

ISBN: (纸本)9781479914173

Embedded systems frequently use FPGAs to perform highly parallel data processing tasks. However, building such a system usually requires specialized hardware design skills with VHDL or Verilog. Instead, this paper presents the VectorBlox MXP Matrix Processor, an FPGA-based soft processor capable of highly parallel execution. Programmed entirely in C, the MXP is capable of executing data-parallel software algorithms at hardware-like speeds. For example, the MXP running at 200MHz or higher can implement a multi-tap FIR filter and output 1 element per clock cycle. MXP's parameterized design lets the user specify the amount of parallelism required, ranging from 1 to 128 or more parallel ALUs. Key features of the MXP include a parallel-access scratchpad memory to hold vector data and high-throughput DMA and scatter/gather engines. To provide extreme performance, the processor is expandable with custom vector instructions and custom DMA filters. Finally, the MXP seamlessly ties into existing Altera and Xilinx development flows, simplifying system creation and deployment.

关键词： Vectors Engines Field programmable gate arrays hardware Registers Finite impulse response filters Clocks

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Scalable NoC-based architecture of neural coding for new efficient associative memories 13

Scalable NoC-based architecture of neural coding for new eff...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jean-Philippe Diguet Marius Strum Nicolas Le Griguer Lydie Caetano Martha Johanna Sepúlveda CNRS Lab-STICC Lorient France Microelectronics Lab.-EPUSP Univ. of São Paulo Brazil UMR6285 Lab-STICC Lorient France

ISBN: (纸本)9781479914173

We present the first NoC-based hardware implementation of Neural Coding (NC), which is a new approach that opens outstanding perspectives for the design of associative memories and learning machines. We first propose optimized architectures of memories and processing elements that allow for an efficient distributed implementation. Then we introduce different NoC architectures to interconnect all elements, it provides the required scalability and takes advantage of parallel transfer opportunities. Performance, cost and energy consumption tradeoffs of various NoC solutions are compared and discussed. Based on previous implementation results, we run systemC-TLM that validate the behavior of the algorithm and of the efficiency of the dedicated architecture. This work demonstrates that this architecture can meet expected requirements in terms of scalability and hierarchy, and consequently that NC-based architectures are compliant with efficient hardware implementations of a new and promising model of associative memories.

关键词： Neurons Encoding Associative memory Computer architecture hardware Vectors Neural networks

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A cyber-physical system approach to artificial pancreas design 13

A cyber-physical system approach to artificial pancreas desi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Mahboobeh Ghorbani Paul Bogdan University of Southern California Los Angeles CA USA

ISBN: (纸本)9781479914173

Healthcare costs in the US are among the highest in the world. Widespread chronic diseases such as diabetes constitute a significant cause of rising healthcare costs. Despite the increased need for smart healthcare systems that monitor patients' body balance, there is no coherent theory that facilitates the design and optimization of efficient and robust cyber physical systems. In this paper, we propose a mathematical model for capturing the dynamics of blood glucose characteristics (e.g., time dependent fractal behavior) observed in real world measurements via fractional calculus concepts. Building on our time dependent fractal model, we propose a novel mathematical model as well as hardware architecture for an artificial pancreas that relies on solving a constrained multi-fractal optimal control problem for regulating insulin injection. We verify the accuracy of our mathematical model by comparing it to conventional nonfractal models using real world measurements and showing that the nonlinear optimal controller based on fractal calculus concepts is superior to nonfractal controllers. We also verified the feasibility of in silico realization of the proposed optimal control algorithm by prototyping on FPGA platform.

关键词： Sugar Blood Insulin Fractals Mathematical model Heuristic algorithms Optimal control

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CMSM: An efficient and effective Code Management for software Managed Multicores 13

CMSM: An efficient and effective Code Management for Softwar...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Ke Bai Jing Lu Aviral Shrivastava Bryce Holton Compiler Microarchitecture Laboratory Arizona State University Tempe Arizona USA

ISBN: (纸本)9781479914173

As we scale the number of cores in a multicore processor, scaling the memory hierarchy is a major challenge. software Managed Multicore (SMM) architectures are one of the promising solutions. In an SMM architecture, there are no caches, and each core has only a local scratchpad memory. If all the code and data of the task mapped to a core do not fit on its local scratchpad memory, then explicit code and data management is required. In this paper, we solve the problem of efficiently managing code on an SMM architecture. We extend the state of the art by: i) correctly calculating the code management overhead, ii) even in the presence of branches in the task, and iii) developing a heuristic CMSM (Code Mapping for software Managed multicores) that results in efficient code management execution on the local scratchpad memory. Our experimental results collected after executing applications from MiBench suite [1] on the Cell SPEs (Cell is an SMM architecture) [2], demonstrate that correct management cost calculation and branch consideration can improve performance by 12%. Our heuristic CMSM can reduce runtime in more than 80% of the cases, and by up to 20% on our set of benchmarks.

关键词： Memory management Multicore processing Interference Switches software Estimation

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Instruction set extensions for Dynamic Time Warping 13

Instruction set extensions for Dynamic Time Warping

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Joseph Tarango Eamonn Keogh Philip Brisk Department of Compuer Science and Engineering University of California Riverside Riverside CA

ISBN: (纸本)9781479914173

Processor specialization through application-specific instruction set customization can significantly improve performance while reducing energy. Due to the costs associated with semiconductor fabrication, specialized processors are only viable for products with high production volumes. The emergence of low-cost sensor-based computing products in recent years has created an urgent need to process time-series data with the utmost efficiency. Although most sensor data is fixed-point, the normalization process-an absolute necessity for highly accurate similarity search of time-series data-converts the data to floating-point in order to avoid a loss in precision. The sensors that collect time-series data are typically connected to low-power microcontrollers or RISC processors sans floating point units. The computational requirements of real-time similarity search would overwhelm such processors. To address this concern, we introduce a specialized instruction set for time-series data mining applications to a 32-bit embedded processor, yielding a 4.87x performance improvement and a 78% reduction in energy consumption compared to a highly optimized software implementation.

关键词： Time complexity Time series analysis Real-time systems Data mining Robot sensing systems Heuristic algorithms software

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On the automatic generation of GPU-oriented software applications from RTL IPs 13

On the automatic generation of GPU-oriented software applica...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Nicola Bombieri Franco Fummi Sara Vinco Dipartimento di Informatica Università di Verona Italy

ISBN: (纸本)9781479914173

Graphics processing units (GPUs) have been explored as a new computing paradigm for accelerating computation intensive applications. In particular, the combination between GPUs and CPU has proved to be an effective solution for accelerating the software execution, by mixing the few CPU cores optimized for serial processing with many smaller GPU cores designed for massively parallel computations. In addition, sustained by the need of low power consumption besides high performance, a recent trend is combining GPUs and CPU onto a single die (e.g., AMD Fusion, Intel Sandy Bridge, NVIDIA Tegra). The good tradeoff between computing capability and power consumption makes the integrated GPUs a promising alternative for accelerating a wide range of software application for embedded systems. Nevertheless, algorithms must be redesigned to take advantage of these architectures and such a manual parallelization often results in being unsatisfactory. This paper presents a methodology to automatically generate software applications for GPUs, by reusing existing and preverified register-transfer level (RTL) intellectual-properties (IPs). The methodology aims at exploiting the intrinsic parallelism of RTL IPs (such as process concurrency and pipeline micro-architecture) for generating the parallel software implementation of the functionality. The experimental results show how the performance obtained by running the RTL functionality as software applications on GPUs outperform those provided by the RTL code mapped into a hardware accelerator.

关键词： Graphics processing units Parallel processing Pipelines IP networks Instruction sets Computer architecture

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Improving polyhedral code generation for high-level synthesis 13

Improving polyhedral code generation for high-level synthesi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Wei Zuo Peng Li Deming Chen Louis-Noël Pouchet Shunan Zhong Jason Cong Beijing Institute of Technology PKU/UCLA Joint Research Institution for Science and Engineering University of Illinois at Urbana-Champaign University of California Los Angeles

ISBN: (纸本)9781479914173

High-level synthesis (HLS) tools are now capable of generating high-quality RTL codes for a number of programs. Nevertheless, for best performance aggressive program transformations are still required to exploit data reuse and enable communication/computation overlap. The polyhedral compilation framework has shown great promise in this area with the development of HLS-specific polyhedral transformation techniques and tools. However, all these techniques rely on polyhedral code generation to translate a schedule for the program's operations into an actual C code that is input to the HLS tool. In this work we study the changes to the state-of-the-art polyhedral code generator CLooG which are required to tailor it for HLS purposes. In particular, we develop various techniques to significantly improve resource utilization on the FPGA. We also develop a complete technique geared towards effective code generation of rectangularly tiled code, leading to further improvements in resource utilization. We demonstrate our techniques on a collection of affine benchmarks, reducing by 2x on average (up to 10x) the area used after high-level synthesis.

关键词： Field programmable gate arrays Optimization Tiles Benchmark testing Table lookup Digital signal processing Measurement

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