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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

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Dimensioning and configuration of EES systems for electric vehicles with boundary-conditioned adaptive scalarization 13

Dimensioning and configuration of EES systems for electric v...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Wanli Chang Martin Lukasiewycz Sebastian Steinhorst Samarjit Chakraborty TUM CREATE Singapore TU Munich Germany

ISBN: (纸本)9781479914173

Electric vehicles (EVs) are widely considered as a solution for efficient, sustainable and intelligent transportation. An electrical energy storage (EES) system is the most important component in an EV in terms of performances and cost. This work proposes an approach for optimal dimensioning and configuration of EES systems in EVs. It is challenging to find optimal design points in the parameter space, which expands exponentially with the number of battery types available and the number of cells that can be implemented for each type. A multi-objective optimization problem is formulated with the driving range, rated power output, installation space and cost as design targets. We report a novel boundary-conditioned adaptive scalarization technique to solve both convex and concave problems. It provides a Pareto surface of evenly distributed Pareto points, presents the group of Pareto points according to different specific requirements from automotive manufacturers and also takes the fact in EES system design into account that the importance of an objective could be nonlinear to its value. Numerical and practical experiments prove that our proposed approach is effective for industry use and produces optimal solutions.

关键词： Batteries Optimization Mathematical model Vehicles Equations Linear programming system analysis and design

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pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment 13

pvFPGA: Accessing an FPGA-based hardware accelerator in a pa...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Wei Wang Miodrag Bolic Jonathan Parri Computer Architecture Research Group University of Ottawa Ottawa Ontario Canada

ISBN: (纸本)9781479914173

In this paper we present pvFPGA, the first system design solution for virtualizing an FPGA-based hardware accelerator on the x86 platform. Our design adopts the Xen virtual machine monitor (VMM) to build a paravirtualized environment, and a Xilinx Virtex-6 as an FPGA accelerator. The accelerator communicates with the x86 server via PCI Express (PCIe). In comparison to the recent accelerator virtualization solutions which primarily intercept and redirect API calls to the hosted or privileged domain's user space, pvFPGA virtualizes an FPGA accelerator directly at the lower device driver level. This gives rise to higher efficiency and lower overhead. In pvFPGA, each unprivileged domain allocates a shared data pool for both user-kernel and inter-domain data transfer. In addition, we propose a new component, the coprovisor, which enables multiple domains to simultaneously access an FPGA accelerator. The experimental results have shown that 1) pvFPGA achieves close-to-zero overhead compared to accessing the FPGA accelerator without the VMM layer, 2) the FPGA accelerator is successfully shared by multiple domains, and 3) distributing different maximum data transfer bandwidths to different domains is achieved by regulating the size of the shared data pool at the split driver loading time.

关键词： Field programmable gate arrays hardware Kernel Virtualization Servers Virtual machine monitors Aerospace electronics

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VarEMU: An emulation testbed for variability-aware software 13

VarEMU: An emulation testbed for variability-aware software

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Lucas Wanner Salma Elmalaki Liangzhen Lai Puneet Gupta Mani Srivastava University of California Los Angeles

ISBN: (纸本)9781479914173

Modern integrated circuits, fabricated in nanometer technologies, suffer from significant power/performance variation across-chip, chip-to-chip and over time due to aging and ambient fluctuations. Furthermore, several existing and emerging reliability loss mechanisms have caused increased transient, intermittent and permanent failure rates. While this variability has been typically addressed by process, device and circuit designers, there has been a recent push towards sensing and adapting to variability in the various layers of software. Current hardware platforms, however, typically lack variability sensing capabilities. Even if sensing capabilities were available, evaluating variability-aware software techniques across a significant number of hardware samples would prove exceedingly costly and time consuming. We introduce VarEMU, an extension to the QEMU virtual machine monitor that serves as a framework for the evaluation of variability-aware software techniques. VarEMU provides users with the means to emulate variations in power consumption and in fault characteristics and to sense and adapt to these variations in software. Through the use (and dynamic change) of parameters in a power model, users can create virtual machines that feature both static and dynamic variations in power consumption. Faults may be injected before or after, or completely replace the execution of any instruction. Power consumption and susceptibility to faults are also subject to dynamic change according to an aging model. A software stack for VarEMU features precise control over faults and provides virtual energy monitors to the operating system and processes. This allows users to precisely quantify and evaluate the effects of variations on individual applications. We show how VarEMU tracks energy consumption according to variation-aware power and aging models and give examples of how it may be used to quantify how faults in instruction execution affect applications.

关键词： hardware Aging Integrated circuit modeling Registers Switching circuits Program processors

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A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters 13

A variability-aware OpenMP environment for efficient executi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Abbas Rahimi Andrea Marongiu Rajesh K. Gupta Luca Benini Department of Computer Science and Engineering UC San Diego La Jolla CA USA Dipartimento di Ingegneria dell'Energia Elettrica e dell'lnformazione Universita di Bologna Bologna Italy

ISBN: (纸本)9781479914173

We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and accuracy-reconfigurable floating-point units (FPUs). The resilient shared-FPUs dynamically characterize FP pipeline vulnerability (FPV) and expose it as metadata to a software scheduler for reducing the cost of error correction. To further reduce this cost, our programming and runtime environment also supports controlled approximate computation through a combination of design-time and runtime techniques. We provide OpenMP extensions (as custom directives) for FP computations to specify parts of a program that can be executed approximately. We use a profiling technique to identify tolerable error significance and error rate thresholds in error-tolerant image processing applications. This information guides an application-driven hardware FPU synthesis and optimization design flow to generate efficient FPUs. At runtime, the scheduler utilizes FPV metadata and promotes FPUs to accurate mode, or demotes them to approximate mode depending upon the code region requirements. We demonstrate the effectiveness of our approach (in terms of energy savings) on a 16-core tightly-coupled cluster with eight shared-FPUs for both error-tolerant and general-purpose error-intolerant applications.

关键词： Pipelines Timing Approximation methods Registers Computer architecture Runtime software

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IVaM: Implicit variant modeling and management for automotive embedded systems 13

IVaM: Implicit variant modeling and management for automotiv...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sebastian Graf Michael Glaß Dominic Wintermann Jürgen Teich Christoph Lauer University of Erlangen-Nuremberg Germany Friedrich-Alexander-Universitat Erlangen-Nurnberg Erlangen Bayern DE AUDI AG Ingolstadt Germany

ISBN: (纸本)9781479914173

In this paper, we propose a graph-based approach for the modeling and efficient analysis of functional variants of a car's electric and electronic (E/E) architecture functionality by combining local technical expert knowledge with global business knowledge. Starting with a variants system specification including a set of task graphs, linear constraints on binary variables are specified for their alternative selection as well as the selection of groups of alternatives called application groups. These constraints may stem from a certain domain knowledge, e. g., entertainment or power train domain, or global constraints. The typically vast space of resulting possible combinations of different selections of alternative behaviors will be termed variant space and those satisfying the set of formulated constraints valid variants. An important result of this paper is that the set of variants, and especially the set of valid variants, do not need to be modeled or stored explicitly but rather implicitly. Nevertheless do we show that using state-of-the-art PB solver techniques, we may determine the set of valid variants very efficiently. Each of these valid variants may subsequently be used as a candidate for design space exploration (DSE) in order to optimize also the mapping of the corresponding task graph functionalities to a final optimized E/E architecture. A real-world case study is provided to demonstrate the capabilities and efficiency of the presented approach on implicit variant modeling and analysis.

关键词： Space exploration Computer architecture hardware software Automotive engineering Business Sensors

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Designing a residential hybrid electrical energy storage system based on the energy buffering strategy 13

Designing a residential hybrid electrical energy storage sys...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Di Zhu Siyu Yue Yanzhi Wang Younghyun Kim Naehyuck Chang Massoud Pedram University of Southern California CA USA Seoul National University Korea

ISBN: (纸本)9781479914173

Due to severe variation in load demand over time, utility companies generally raise electrical energy price during periods of high load demand. A grid-connected hybrid electrical energy storage (HEES) system can help residential users lower their electric bills by storing energy during low-price hours and releasing the stored energy during high-price hours. A HEES system consists of different types of electrical energy storage (EES) elements, utilizing the benefits of each type while hiding their weaknesses. This paper presents a residential energy management system to maximize the annual profits on residential electric bills, based on a HEES system comprised of a lead-acid battery bank as the main storage bank and a Li-ion battery bank as the energy buffer. We first derive the optimal daily energy management policy based on energy buffering to minimize the daily energy cost. Next, we find the near-optimal design specifications of the energy management system, aiming at maximizing the amortized annual profits under practical constraints. We show that this system achieves averagely 11.10% more profits compared to the none-buffering HEES system.

关键词： Batteries Lead Discharges (electric) Pricing Energy management Supercapacitors

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APECS: An AADL and polychrony based embedded computing system design environment with an elevator control case study

APECS: An AADL and polychrony based embedded computing syste...

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Matthew Anderson Sandeep K. Shukla Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA

ISBN: (纸本)9781479909049

Architecture Analysis and Design Language (AADL) is a standard that originated in the avionics domain, but is now being used in avionics and other critical distributed real-time embedded system design. AADL provides a formal notation and semantics for capturing an entire distributed platform architecture (hardware components, protocols, and software architecture annotated with properties including real-time measures). The software architecture captures the location and structure of processes, threads, and the data and control flow specifications. The behavior of the processes/threads/subprograms are provided via a native state machine language or via a behavioral annex. Schedulability, performance, and other system level properties can be analyzed using various tools. Even code synthesis - targeting the formally described platform components and middleware can be enabled if the threads/processes can be behaviorally specified. In this paper, we describe our methodology and a design environment both named APECS. APECS is meant for enabling an end-to-end distributed real-time embedded system design which integrates a number of existing tools, and our own polychronous language based specification language MRICDF, and the corresponding synthesis methodology. While the environment is in an advanced stage of development, we illustrate the architecture of the design environment, and illustrate the methodology through a non-trivial case study. The case study uses APECS methodology and tools in developing the distributed control for a 4 bank elevator system in a 5 story building. We posit this paper as a methodology and tool paper and it is written in a tutorial spirit rather than a paper describing new theories or algorithms.

关键词： Analytical models Real-time systems Program processors Ports (Computers) Computer architecture Standards

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APECS: An AADL and polychrony based embedded computing system design environment with an elevator control case study 13

APECS: An AADL and polychrony based embedded computing syste...

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Proceedings of the Eleventh ACM/IEEE international conference on Formal Methods and Models for codesign

ISBN: (纸本)9781479909056

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software Energy Optimization Through Fine-Grained Function-Level Voltage and Frequency Scaling 12

Software Energy Optimization Through Fine-Grained Function-L...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Brandolese, Carlo Fornaciari, William Politecn Milan I-20133 Milan Italy

ISBN: (纸本)9781450314268

This paper presents a methodology and a toolchain to perform estimation and optimization of the energy consumption associated to software execution on tiny embedded systems. The estimation phase is based on an ISA-level characterization of the target processor, while the optimization phase is made combining the estimation process with design space exploration in order to exploit fine-grained dynamic voltage and frequency scaling. The proposed approach operates at compile-time, with the granularity of single C functions and almost automatically augments the source code.

关键词： Power Optimization Embedded systems

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synthesis of Optimized hardware Transactors from Abstract Communication Specifications 12

Synthesis of Optimized Hardware Transactors from Abstract Co...

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10th ACM international conference on hardware/software-codesign and system synthesis

作者： Lee, Dongwook Park, Hyungman Gerstlauer, Andreas Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781450314268

Increasing system complexity and heterogeneity make system integration and communication synthesis a growing concern. Even with transaction-level modeling and high-level synthesis of hardware, communication interfaces still have to be manually designed at a low protocol level. To address this challenge, we present a design flow for automatic synthesis of hardware transactors, which realize abstractly specified communication semantics OH top of protocol-level transactions. Transactor synthesis is tightly coupled with high-level synthesis of computation for integrated computation/communication co-design of complete hardware processors, thus establishing a seamless path from abstract system specifications down to hardware implementations in synthesizable RTL. The flow supports a generic set of communication semantics and target implementations, where transactors are custom-generated for a specific application and architecture combination. Furthermore, we develop protocol stack optimizations that reduce the area and performance overhead of synthesized communication interfaces. We have applied our synthesis flow to several industrial-strength examples under various communication settings. Results show that synthesized interfaces are comparable to manual designs in terms of area and latency, where protocol stack optimizations can reduce area and latency overhead by up to 77% and 21%, respectively.

关键词： transactor hardware synthesis interface synthesis

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