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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 852 条记录，以下是31-40 订阅

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FPGA-Based hardware Optimization and Implementation of YOLOv4-tiny 3

FPGA-Based Hardware Optimization and Implementation of YOLOv...

引用

3rd international conference on Communications, Information system, and Data Science, CISDS 2024

作者： Wang, Kai Bai, Yanhong Li, Xiaosong Department of Electronic Information Engineering Taiyuan University of Science and Technology Taiyuan030024 China Department of Intelligent Manufacturing Industry Shanxi University of Electronic Science and Technology Linfen041000 China

ISBN: (数字)9781510688322

ISBN: (纸本)9781510688315

To address the challenges associated with the YOLOv4-Tiny algorithm's complex structure, high computational resource requirements, and extensive parameter count-which collectively impede efficient FPGA deployment-we propose a hardware-software co-optimization strategy. This approach replaces the YOLOv4-Tiny backbone with the MobileNetv1 network and integrates the Convolutional Block Attention Module (CBAM) into the enhanced feature extraction network. Channel pruning is applied to streamline the network structure, and weights and biases are quantized to 16-bit fixed-point representations. Compared to the original YOLOv4-Tiny, this optimized network reduces parameters by 40% while retaining nearly identical recognition *** high-level synthesis tools, we generate FPGA IP cores, design a parallel pipelined convolutional architecture, and implement inter-layer blocking between convolutional layers to enhance computational efficiency. This improved algorithm is deployed on a Zynq-7020 FPGA chip. Experimental results show that the optimized algorithm achieves a computational performance of 43.4 GOP/s, offering a speedup of 1.6 to 4.1 times compared to existing studies, with an energy efficiency ratio 4.8 to 10.7 times greater than current implementations. These findings indicate that the proposed strategy significantly improves algorithm deployment efficiency on resource-limited FPGA platforms. © 2025 SPIE.

关键词： High level synthesis

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Special Session: Emerging Architecture Design, Control, and Security Challenges in software Defined Vehicles

Special Session: Emerging Architecture Design, Control, and ...

引用

2024 international conference on hardware/software codesign and system synthesis

作者： El-Fatyany, Aya Wang, Xiaohang Duggirala, Parasara Sridhar Chakraborty, Samarjit Pasricha, Sudeep Singh, Amit Kumar Zhejiang Univ Hangzhou Peoples R China Menoufia Univ Shibin Al Kawm Egypt UNC Chapel Hill Chapel Hill NC USA Colorado State Univ Ft Collins CO USA Univ Essex Colchester England

ISBN: (纸本)9798350356403;9798350356397

software Defined Vehicles (SDVs) represent a paradigm shift in the automotive industry, where vehicles are increasingly controlled and managed through software, while relying less on mechanical and hardware components. While this allows considerable flexibility in the introduction of new "smart" features and fast tracks innovations in multiple domains, it also creates new challenges and opportunities in architecture design, control, and security. By adopting modular architectures, adaptive control strategies, and robust security measures, SDVs can pave the way for a safer and more efficient future of transportation. In this paper, we cover perspectives from both, industry and academia, in this area. They provide embedded systems researchers an overview of recent developments and emerging challenges in SDV from the perspective of architecture design, control, and security. The emerging challenges also set the foundations for future research in this domain.

关键词： software defined vehicles (SDVs) Architecture design Control Robustness Security

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Work-in-Progress: BloCirNN: An Efficient software/hardware codesign Approach for Neural Network Accelerators with Block-Circulant Matrix

Work-in-Progress: BloCirNN: An Efficient Software/hardware C...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis part of the Embedded systems Week (ESWEEK)

作者： Qin, Yunji Gong, Lei Zheng, Zhendong Wang, Chao Univ Sci & Technol China Sch Comp Sci & Technol Hefei Peoples R China

ISBN: (数字)9781665472944

ISBN: (纸本)9781665472944

Nowadays, the scale of deep neural networks is getting larger and larger. These large-scale deep neural networks are both compute and memory intensive. To overcome these problems, we use block-circulant weight matrices and Fast Fourier Transform (FFT) to compress model and optimize computation. Compared to weight pruning, this method does not suffer from irregular networks. The main contributions of this paper include the implementation of a convolution module and a fully-connected module with High-Level synthesis (HLS), deployment and performance test on FPGA platform. We use AlexNet as a case study, which demonstrates our design is more efficient than the FPGA2016.

关键词： block-circulant matrix compression FPGA Accelerator

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Work-in-Progress: Towards the Application of Flask Security Architecture to SoC Design 12

Work-in-Progress: Towards the Application of Flask Security ...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hategekimana, Festus Bobda, Christophe Univ Arkansas Fayetteville AR 72701 USA

ISBN: (纸本)9781450351850

In this work, we explore a security reference monitor (RM) design which borrows from the Flask security architecture. Our RM design goal is to achieve complete mediation by checking and verifying the authority and the authenticity of every access to every system object in systems-on-chip (SoCs). Access decisions are administered by a security logic "server" implemented as an extension of the peripheral bus. Initial results show a minimal increase in resource overhead and no significant impact on the performance.

关键词： systems-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs) Trojan hardware sandbox Secure Execution Component Authentication Process

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Work-in-Progress: High-Performance Systolic hardware Accelerator for RBLWE-based Post-Quantum Cryptography

Work-in-Progress: High-Performance Systolic Hardware Acceler...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis part of the Embedded systems Week (ESWEEK)

作者： Bao, Tianyou Imana, Jose L. He, Pengzhou Xie, Jiafeng Villanova Univ Dept Elect Comp Engn Villanova PA USA Univ Complutense Dept Comp Architecture Automat Madrid Spain

ISBN: (数字)9781665472944

ISBN: (纸本)9781665472944

Ring-Binary-Learning-with-Errors (RBLWE)-based post-quantum cryptography (PQC) is a promising scheme suitable for lightweight applications. This paper presents an efficient hardware systolic accelerator for RBLWE-based PQC, targeting highperformance applications. We have briefly given the algorithmic background for the proposed design. Then, we have transferred the proposed algorithmic operation into a new systolic accelerator. Lastly, field-programmable gate array (FPGA) implementation results have confirmed the efficiency of the proposed accelerator.

关键词： Polynomial multiplication PQC RBLWE systolic hardware accelerator

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Work-in-Progress: What to Expect of Early Training Statistics? An Investigation on hardware-Aware Neural Architecture Search

Work-in-Progress: What to Expect of Early Training Statistic...

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ACM/IEEE international conference on hardware/software codesign and system synthesis part of the Embedded systems Week (ESWEEK)

作者： Luo, Xiangzhong Liu, Di Kong, Hao Huai, Shuo Chen, Hui Liu, Weichen Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore Nanyang Technol Univ HP NTU Digital Mfg Corp Lab Singapore Singapore

ISBN: (数字)9781665472944

ISBN: (纸本)9781665472944

Neural architecture search (NAS) is an emerging paradigm to automate the design of top-performing deep neural networks (DNNs). Specifically, the increasing success of NAS is attributed to the reliable performance estimation of different architectures. Despite significant progress to date, previous relevant methods suffer from prohibitive computational overheads. To avoid this, we propose an effective yet computationally efficient proxy, namely Trained Batchwise Estimation (TBE), to reliably estimate the performance of different architectures using the early batchwise training statistics. We then integrate TBE into the hardware-aware NAS scenario to search for hardware-efficient architecture solutions. Experimental results clearly show the superiority of TBE over previous relevant state-of-the-art approaches.

关键词： Training Deep learning Neural networks Estimation Computer architecture Reliability

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Work-in-Progress: Remote Detection of Unauthorized Activity via Spectral Analysis 12

Work-in-Progress: Remote Detection of Unauthorized Activity ...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Karabacak, Fatih Ogras, Umit Ozev, Sule Arizona State Univ Sch ECEE Tempe AZ 85281 USA

ISBN: (纸本)9781450351850

Unauthorized hardware or firmware modifications, known as trojans, can steal information, drain the battery, or damage IoT devices. This paper presents a stand-off self-referencing technique for detecting unauthorized activity. The proposed technique processes involuntary electromagnetic emissions on a separate hardware, which is physically decoupled from the device under test. When the device enter the test mode, it runs a predefined application repetitively with a fixed period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operation bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicates the presence of unknown (unauthorized) activity. Experiments based on hardware measurements show that the proposed technique achieves close to 100% detection accuracy at up to 120 cm distance.

关键词： IoT Security hardware/Firmware Trojan Detection EM Emission

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hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis

Hardware synthesis from coarse-grained dataflow specificatio...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Jung, H Ha, S Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151744 South Korea

ISBN: (纸本)1581139373

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

关键词： HW/SW codesign system level design dataflow graph(DFG) VHDL autonomic hardware synthesis

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A core flight software system 05

A core flight software system

引用

international conference on hardware/software codesign and system synthesis

作者： Wilmot, J Goddard Space Flight Ctr Flight Software Branch Greenbelt MD 20771 USA

ISBN: (纸本)1595931619

No two flight missions are alike, hence, development and on-orbit software costs are high. software portability and adaptability across hardware platforms and operating systems has been minimal at best. Standard interfaces across applications and/or common applications are almost non-existent. To reduce flight software costs, these issues must be addressed. This presentation describes how the Flight software Branch at Goddard Space Flight Center has architected a solution to these problems.

关键词： software operating system interfaces

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Work-in-Progress: Exploring Fast and Slow Memories in HMP Core Types 12

Work-in-Progress: Exploring Fast and Slow Memories in HMP Co...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Donyanavard, Bryan Monazzah, Amir Mandi Hosseini Muck, Tiago Dutt, Nikil Univ Calif Irvine Irvine CA 92697 USA Sharif Univ Technol Tehran Iran

ISBN: (纸本)9781450351850

Studies have shown memory and computational needs vary independently across applications. Recent work has explored using hybrid memory technology (SRAM+NVM) in on-chip memories of multicore processors (CMPs) to support the varied needs of diverse workloads. Such works suggest architectural modifications that require supplemental management in the memory hierarchy. Instead, we propose to deploy hybrid memory in a manner that integrates seamlessly with the existing heterogeneous multicore (HMP) architectural model, and therefore does not require any architectural modification, simply the integration of different memory technologies on-chip. We evaluate platforms with a combination of fast (SRAM cache) and slow (STT-MRAM cache) core-types for mobile workloads.

关键词： SPM scratchpad Memory hardware/software memory management many-core architectures virtualization

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