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Dominator homomorphism based code matching for source-level simulation of embedded software 11

Dominator homomorphism based code matching for source-level ...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Stattelmann, Stefan Bringmann, Oliver Rosenstiel, Wolfgang FZI Forschungszentrum Informatik Haid-und-Neu-Str. 10-14 D-76131 Karlsruhe Germany University of Tuebingen Sand 13 D-72076 Tuebingen Germany

ISBN: (纸本)9781450307154

Relating optimized binary code and the source-level statements from which it was created can be challenging if an optimizing compiler was used to create the machine code. Moreover, this relation is crucial if a compiler-optimized program must be debugged or results from a low-level analysis need to be mapped to the source code to perform manual optimizations. Existing approaches for the debugging of optimized code usually require pervasive changes in the compiler and hence are not available for all architectures. Methods for analyzing non-functional properties of software components in complex systems (i.e. execution time and power consumption) often have similar constraints, if compiler optimizations are supported at all. This paper proposes two novel concepts to overcome these issues. To precisely relate source-level statements with the respective compiler-generated machine code, a method to reconstruct and disambiguate debug information is presented. Based on this information, an instrumentation technique is introduced which allows accurately simulating the execution of optimized binary code at the source code level. Experimental results show that by using this technique, arbitrary low-level properties of software components can be evaluated in a fast and accurate manner without running the software on the actual target hardware. Copyright 2011 ACM.

关键词： Binary codes

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Constraint-driven synthesis and tool-support for flexray-based automotive control systems 11

Constraint-driven synthesis and tool-support for flexray-bas...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Schneider, Reinhard Goswami, Dip Zafar, Sohaib Chakraborty, Samarjit Lukasiewycz, Martin TU Munich Germany TUM CREATE Singapore

ISBN: (纸本)9781450307154

Emerging bus protocols such as FlexRay provide an expedient platform for the design of automotive control systems due to its high bandwidth and deterministic temporal behavior. However, the choice of suitable platform parameters such as task and message schedules becomes a challenging design problem as the protocol is complex in nature and enforces a tight coupling between local task schedules on ECUs and global bus schedules. Although there exist several commercial off-the-shelf (COTS) design tools for FlexRay and control systems, current tools do not provide any mechanism for automatically synthesizing the platform parameters from the controller specifications. In this work we synthesize controllers subject to specified control goals while taking into account platform-specific properties. In particular, we translate the timing constraints derived from the control design into platform constraints that need to be satisfied by the control-related tasks and messages. For this purpose, we formulate and solve a constraint satisfaction problem (CSP) to synthesize feasible platform parameters that can be realized by the underlying operating systems and the FlexRay bus. Our design flow may be easily integrated with existing FlexRay design tools and will significantly ease (and automate) the existing design process. We show the applicability of our results by implementing two automotive control systems on a hardware-in-the-Loop (HiL) setup and study how different bus configurations affect the controller synthesis and the choice of platform parameters. Copyright 2011 ACM.

关键词： Cyber Physical system

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IOPT Petri Net State Space Generation Algorithm with Maximal-Step Execution Semantics

IOPT Petri Net State Space Generation Algorithm with Maximal...

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9th IEEE international conference on Industrial Informatics (INDIN)

作者： Pereira, Fernando Moutinho, Filipe Gomes, Luis Campos-Rebelo, Rogerio ISEL Inst Super Engenharie Lisboa Lisbon Portugal Univ Nova Lisboa CTS Caparica Portugal

ISBN: (纸本)9781457704345

This paper presents an algorithm to efficiently generate the state-space of systems specified using the IOPT Petri-net modeling formalism. IOPT nets are a non-autonomous Petri-net class, based on Place-Transition nets with an extended set of features designed to allow the rapid prototyping and synthesis of system controllers through an existing hardware-software co-design framework. To obtain coherent and deterministic operation, IOPT nets use a maximal-step execution semantics where, in a single execution step, all enabled transitions will fire simultaneously. This fact increases the resulting state-space complexity and can cause an arc "explosion" effect. Real-world applications, with several million states, will reach a higher order of magnitude number of arcs, leading to the need for high performance state-space generator algorithms. The proposed algorithm applies a compilation approach to read a PNML file containing one IOPT model and automatically generate an optimized C program to calculate the corresponding state-space.

关键词： Algorithm design and analysis C language C program Fires Firing Generators IOPT Petri net generation algorithm IOPT Petri-net modeling formalism PNML file Petri nets Semantics software system recovery arc explosion effect compilation approach computational complexity formal verification hardware-software codesign framework input-output place-transition Petri nets maximal-step execution semantics model checking approach place-transition nets program compilers rapid prototyping state-space complexity

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Design entropy concept: A measurement for complexity 11

Design entropy concept: A measurement for complexity

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Benjamin Menhorn Frank Slomka Institute for Embedded Systems/Real-Time Systems Ulm University Germany

ISBN: (纸本)9781450307154

In general, this work will deal with measuring complexity. The focus question is towards addressing complexity in an adequate way. This work concentrates on digital circuits and digital hardware. For this field of computer science the complexity for circuits will be calculated. Therefore, a new complexity measure will be introduced, called design entropy. It allows a mathematical calculation of complexity resulting in figures. These allow a direct evaluation and comparison between different systems and realizations. The application and important capabilities of this measurement will be demonstrated on different examples.

关键词： Complexity theory Entropy Computer architecture hardware Microprocessors Mathematical model Transistors

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CODES+ISSS keynote: To alert, rescue and recover: Critical information technologies for managing mega disasters

CODES+ISSS keynote: To alert, rescue and recover: Critical i...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jane W. S. Liu Institute of Information Science and Research Center for Information Technology Innovations Academia Sinica Taiwan

This talk will discuss why despite recent advances, state-of-the-art disaster management IT infrastructures and information systems are not as effective as they should be for managing mega calamitous events of unforeseen sizes and severity. It will then discuss critical gaps in information technology. Examples include methodologies, tools and middleware for: ▪ Exploitation of complementary network technologies to prevent communication failures during disasters; ▪ Flexible and responsive management of logical connectivity and information flow among information sources, fusion modules, applications and end-users, providing them with support for pub/sub messaging, syndication and feed services, dynamic event-triggered messaging and so on; ▪ Trustworthy information brokerage services for safe and responsive emergency access and flow control of information from independently developed information sources owned by government agencies, businesses, institutions, NGOs, communities, private property owners and individuals; ▪ Common models and views, open standard interfaces and API functions to enable independent development of disaster management applications and services; ▪ Advanced disaster management applications and services.

关键词： Information technology Information science Disaster management Real time systems Awards activities software Information systems

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Session details: Tools and algorithms for exploration and synthesis of distributed embedded systems 11

Session details: Tools and algorithms for exploration and sy...

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Proceedings of the seventh IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Hiroyuki Tomiyama Todor Stefanov Ritsumeikan University Leiden University

No abstract available.

ISBN: (纸本)9781450307154

No abstract available.

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system-level design exploration for 3-D stacked memory architectures 11

System-level design exploration for 3-D stacked memory archi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chi-Hung Lin Wen-Tsan Hsieh Hsien-Ching Hsieh Chun-Nan Liu Jen-Chieh Yeh Information and Communications Research Laboratories Industrial Technology Research Institute Hsinchu Taiwan

ISBN: (纸本)9781450307154

Summary form only given. Traditional technology scaling of semiconductor chips followed Moore's Law. However, the transistor performance improvement will be limited, and designer will not see doubling of frequency every two years. Recently, three-dimension integrated circuits (3D IC) that employ the vertically through-silicon vias (TSVs) for connecting each of dies have been proposed. It is an alternative solution to existent Package-on-Package (PoP) and system-in-Package (SiP) processes. There are many benefits by using TSV-based 3-D integration technologies: (1) more functionality can be integrated into a small silicon space for form factor reduction, (2) circuit delay can be improved by using TSVs due to the shorter interconnect and reduced parasitic capacitance/inductance, (3) different components with incompatible manufacturing process (i.e. Logic, DRAM, Flash, etc) can be combined in single 3-D IC for heterogeneous integration. In addition, there are many 3-D multi-core or many-core architectures are discussed recently. Comparing with traditional two-dimension multi-core or many-core architectures, the major difference is memory bandwidth problem can be addressed by stacked memory architecture. Intel has good demonstration through the teraflops microprocessor chip which is an 80-core design with memory-on-logic architecture. And, each core connects to a 256KB SRAM with 12GB/s bandwidth. Although 3-D stacking technology can bring us many benefits for next generation integrated circuits, it comes with many problems and challenges in system-level design. For instance, 3-D IC designs will deal with serious challenges in design space exploration and system validation. For most designs, the number of TSV will be the most critical limitation that should be considered carefully. Besides, system design by 3-D IC will become more and more complex, and it needs a full system-level solution to face the performance, number of TSV, and power issues of 3D-IC. Furthermore, it

关键词： Through-silicon vias Integrated circuit modeling Stacking Multicore processing Random access memory

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hardware/software co-design for high performance computing: Challenges and opportunities 10

Hardware/software co-design for high performance computing: ...

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Hu, X. Sharon Murphy, Richard C. Dosanjh, Sudip Olukotun, Kunle Poole, Stephen Department of Computer Science and Engineering University of Notre Dame Notre Dame IN United States Scalable Computer Architecture Department Sandia National Laboratories Albuquerque NM United States Computer and Software Systems Department Sandia National Laboratories Albuquerque NM United States Department of Electrical Engineering Stanford University Stanford CA United States Computational Sciences Division Oak Ridge National Lab Oak Ridge TN United States

ISBN: (纸本)9781605589053

This special session aims to introduce to the hardware/software codesign community challenges and opportunities in designing high performance computing (HPC) systems. Though embedded system design and HPC system design have traditionally been considered as two separate areas of research, they in fact share quite some common features, especially as CMOS devices continue along their scaling trends and the HPC community hits hard power and energy limits. Understanding the similarities and differences between the design practices adopted in the two areas will help bridge the two communities and lead to design tool developments benefiting both communities.

关键词： hardware-software codesign

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parSC: Synchronous parallel systemC simulation on multi-core host architectures 10

parSC: Synchronous parallel SystemC simulation on multi-core...

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Schumacher, Christoph Leupers, Rainer Petras, Dietmar Hoffmann, Andreas Institute for Integrated Signal Processing Systems RWTH Aachen University Germany Synopsys Inc. Aachen Germany

ISBN: (纸本)9781605589053

Time-consuming cycle-accurate MPSoC simulation is often needed for debugging and verification. Its practicability is put at risk by the growing MPSoC complexity. This work presents a conservative synchronous parallel simulation approach along with a systemC framework to accelerate tightly-coupled MPSoC simulations on multi-core hosts. Key contribution is the implementation strategy, which utilizes techniques from the high-performance computing domain. Results show speed-ups of up to 4.4 on four host cores.

关键词： system-on-chip

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hardware/software optimization of error detection implementation for real-time embedded systems 10

Hardware/software optimization of error detection implementa...

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Lifa, Adrian Eles, Petru Peng, Zebo Izosimov, Viacheslav Linköping University Linköping Sweden Embedded Intelligent Solutions Linköping Sweden

ISBN: (纸本)9781605589053

This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when implemented in hardware, error detection is deployed on static reconfigurable FPGAs, while the second one considers partial dynamic reconfiguration capabilities of the FPGAs.

关键词： Error detection

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