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Statistical approach in a system level methodology to deal with process variation 10

Statistical approach in a system level methodology to deal w...

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Sanz Pineda, Concepción Prieto, Manuel Gómez, José Ignacio Tenllado, Christian Catthoor, Francky Dpto. de Arquitectura de Computadores Y Automática Universidad Complutense de Madrid Madrid 28040 Spain Inter-University Microelectronics Center IMEC Leuven 3001 Belgium

ISBN: (纸本)9781605589053

The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of both energy consumption and performance. In this context, developing variation aware design methodologies becomes a must. These techniques should provide better performance-energy balances while the percentage of faulty products keeps controlled. Furthermore, it would be advisable to consider adaptations of the system during lifetime, in order to provide robustness against ageing. In this paper we propose a design approach which tackles process variation on the memory system by using multimode memories. At design time we perform a heuristic exploration using probabilistic models of these memories, which generates a set of system configurations that minimize energy consumption for a given set of timing constraints. The percentage of systems that will satisfy these deadlines, even under process variation, is taken as a design parameter. Additionally, if system monitors are available, a setup stage optimizes the initial set of configurations for the actual memory parameters. Our simulations show that this methodology provides significant energy savings while still meeting timing constraints. © 2010 ACM.

关键词： Energy utilization

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An elastic software Cache with fast prefetching for motion compensation in video decoding 10

An elastic software Cache with fast prefetching for motion c...

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Chao, Ping Lin, Youn-Long Department of Computer Science National Tsing Hua University Hsin-Chu 30013 Taiwan

ISBN: (纸本)9781605589053

Real-time decoding of ultrahigh resolution video using multicore architectures is important for future embedded systems. However, memory bandwidth is still a bottleneck of system performance. Video coding performs irregular DRAM access resulting in very low and unstable efficiency. The conventional cache approach is insufficient because it reduces only the redundant accesses to data that has already been fetched during prior-macroblock decoding. We present an Elastic software Cache (ESC) for ultrahigh resolution video decoding on Scratchpad Memory (SPM)-based systems. Utilizing access region analysis, our latency-optimized prefetching scheme rearranges accesses to minimize both data redundancy and DRAM access latency. Compared to the conventional cache approach, our scheme requires only 4.6 Kbytes of SPM space but it can save up to 25% of memory access cycles resulting in both higher performance and lower power.

关键词： Decoding

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Towards a synthesis semantics for systemC channels 10

Towards a synthesis semantics for SystemC channels

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Grüttner, Kim Kleen, Henning Oppenheimer, Frank Rettberg, Achim Nebel, Wolfgang OFFIS Institute for Information Technology Escherweg 2 26121 Oldenburg Germany Department of Computer Science Faculty II Carl von Ossietzky University Oldenburg Ammerländer Heerstrasse 114-118 26111 Oldenburg Germany

ISBN: (纸本)9781605589053

In this paper we propose a synthesis semantics for systemC™ channels, which contribute to a clear separation between computation (algorithm) and communication, whereas communication related parts are modelled through either primitive or hierarchical channels. We present a synthesisable replacement for systemC primitive channels that allows deterministic access scheduling and user-constrained refinement for HW/HW and HW/SW communication. We demonstrate the feasibility of our approach through synthesis and exploration of a communication intensive packet switch design under consideration of different configurations and communication refinements.

关键词： Semantics

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Improving platform-based system synthesis by satisfiability Modulo theories solving 10

Improving platform-based system synthesis by satisfiability ...

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Reimann, Felix Glab, Michael Haubelt, Christian Eberl, Michael Teich, Jürgen University of Erlangen Nuremberg Germany

ISBN: (纸本)9781605589053

Due to the ever increasing system complexity, deciding whether a given platform is sufficient to implement a set of applications under given constraints becomes a serious bottleneck in platform-based design. As a remedy, the work at hand proposes a novel automatic platform-based system synthesis procedure, inspired by techniques developed in the context of automatic system verification known as Satisfiability Modulo Theories. It tightly couples the computation of a feasible allocation and binding with nonfunctional constraint checking where, in contrast to existing approaches, not only linear constraints but even nonlinear constraints are supported. This allows to efficiently prove whether there exists a feasible implementation of a set of applications on the given platform with respect to both, functional and nonfunctional constraints. Moreover, an approach for early learning based on feasibility checking of partial implementations is proposed that can signifiantly improve the synthesis runtime, especially in case the selected platform imposes stringent constraints on the implementation. The effectiveness of this approach is shown for an automotive ECU network design that requires Modular Performance Analysis to ensure non-functional nonlinear timing constraints.

关键词： Formal logic

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An introduction to the systemC synthesis subset standard 10

An introduction to the SystemC synthesis subset standard

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Coussy, Philippe Takach, Andres McNamara, Michael Meredith, Mike Université de Bretagne-Sud Rue de Saint Maude Lorient Cedex 56321 France Mentor Graphics 8005 SW Boeckman Rd. Wilsonville OR 97070 United States Cadence 2655 Seely Avenue San Jose CA 95134 United States Forte Design Systems 16150 NE 85th Street Redmond WA 98052 United States

ISBN: (纸本)9781605589053

High-level synthesis (HLS) offers the prospect of improving the productivity digital system design and the quality of the resulting implementations. Designing at higher levels of abstraction is a natural way for coping with system design complexity, for verifying earlier in the design process and for increasing design reuse [1][2][7]. OSCI's synthesis working group (SWG) [3] has led the effort of defining the synthesis subset for systemC that is suitable for HLS. Draft version 1.3 [4] of the document was released for public review in August 2009. While still in draft form, the released document provides guidance to both tool providers and users on the subset that is being proposed and the ability to provide feedback to the SWG on the draft. This tutorial will provide a brief introduction and three case studies on the use of HLS and the current systemC synthesis subset draft for hardware design of digital systems.

关键词： High level synthesis

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FEMU: A firmware-based emulation framework for SoC verification 10

FEMU: A firmware-based emulation framework for SoC verificat...

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Li, Hao Tong, Dong Huang, Kan Cheng, Xu Microprocessor Research and Development Center Peking University Beijing China

ISBN: (纸本)9781605589053

Full-system emulation on FPGA(Field-Programmable Gate Array) with real-world workloads can enhance the confidence of SoC(system-on-Chip) design. However, since FPGA emulation requires complete implementation of key modules and provides weak visibility, it is time-consuming. This paper proposes FEMU, a hybrid firmware/hardware emulation framework for SoC verification. The core of FEMU is implemented by transplanting QEMU, a full-system emulator, from OS level to BIOS level, so we can directly emulate devices upon hardware. Moreover, FEMU provides programming interfaces to simplify device modeling in firmware. Based on an auxiliary set of hardware modules, FEMU allows hybrid full-system emulation with the combination of real hardware and emulated firmware model. Therefore, FEMU can facilitate full-system emulation in three aspects. First, FEMU enables full-system emulation with the minimum hardware implementation, so the DUT (Design Under Test) module can be verified under target application as early as possible. Second, by comparing the execution traces generated using real hardware and emulated firmware model, respectively, FEMU helps locate and fix bugs occurred in the full-system emulation. Third, by replacing un-verified hardware modules with emulated firmware models, FEMU helps isolating design issues in multiple modules. In a practical SoC project, FEMU helped us identify several design issues in full-system emulation. In addition, the evaluation results show that the emulation speed of FEMU is comparable with QEMU after transplantation.

关键词： system-on-chip

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A holistic approach to network-on-chip synthesis 10

A holistic approach to network-on-chip synthesis

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Leary, Glenn Chatha, Karam S. Department of CSE Arizona State University P.O. Box 875406 Tempe AZ 85287-5406 United States

ISBN: (纸本)9781605589053

Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor system-on-Chip architectures. synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.

关键词： Network-on-chip

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Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming 10

Automatic parallelization of embedded software using hierarc...

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Cordes, Daniel Marwedel, Peter Mallik, Arindam Informatik Centrum Dortmund Joseph-von-Fraunhofer-Str. 20 Dortmund Germany Imec Belgium Kapeldreef 75 Leuven Belgium

ISBN: (纸本)9781605589053

The last years have shown that there is no way to disregard the advantages provided by multiprocessor system-on-Chip (MPSoC) architectures in the embedded systems domain. Using multiple cores in a single system enables to close the gap between energy consumption, problems concerning heat dissipation, and computational power. Nevertheless, these benefits do not come for free. New challenges arise, if existing applications have to be ported to these multiprocessor platforms. One of the most ambitious tasks is to extract efficient parallelism from these existing sequential applications. Hence, many parallelization tools have been developed, most of them are extracting as much parallelism as possible, which is in general not the best choice for embedded systems with their limitations in hardware and software support. In contrast to previous approaches, we present a new automatic parallelization tool, tailored to the particular requirements of the resource constrained embedded systems. Therefore, this paper presents an algorithm which automatically steers the granularity of the generated tasks, with respect to architectural requirements and the overall execution time reduction. For this purpose, we exploit hierarchical task graphs to simplify a new integer linear programming based approach in order to split up sequential programs in an efficient way. Results on real-life benchmarks have shown that the presented approach is able to speed sequential applications up by a factor of up to 3.7 on a four core MPSoC architecture.

关键词： Embedded systems

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hardware/software co-design for high performance computing: Challenges and opportunities

Hardware/software co-design for high performance computing: ...

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作者： Hu, X. Sharon Murphy, Richard C. Dosanjh, Sudip Olukotun, Kunle Poole, Stephen Department of Computer Science and Engineering University of Notre Dame Notre Dame IN United States Scalable Computer Architecture Department Sandia National Laboratories Albuquerque NM United States Computer and Software Systems Department Sandia National Laboratories Albuquerque NM United States Department of Electrical Engineering Stanford University Stanford CA United States Computational Sciences Division Oak Ridge National Lab. Oak Ridge TN United States

ISBN: (纸本)9781605589053

This special session aims to introduce to the hardware/software codesign community challenges and opportunities in designing high performance computing (HPC) systems. Though embedded system design and HPC system design have traditionally been considered as two separate areas of research, they in fact share quite some common features, especially as CMOS devices continue along their scaling trends and the HPC community hits hard power and energy limits. Understanding the similarities and differences between the design practices adopted in the two areas will help bridge the two communities and lead to design tool developments benefiting both communities. © 2010 ACM.

关键词： hardware-software codesign

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system-level reliability modeling for MPSoCs 10

System-level reliability modeling for MPSoCs

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Xiang, Yun Chantem, Thidapat Dick, Robert P. Hu, X. Sharon Shang, Li EECS Department University of Michigan Ann Arbor MI 48109 United States CSE Department University of Notre Dame Notre Dame IN 46556 United States ECE Department University of Colorado Boulder CO 80309 United States

ISBN: (纸本)9781605589053

The reliability of multi-processor systems-on-chip (MPSoCs) is affected by several inter-dependent system-level and physical effects. Accurate and fast reliability modeling is a primary challenge in the design and optimization of reliable MPSoCs. This paper presents a reliability modeling framework that integrates device-, component-, and system-level models. This framework contains modules for electromigration, time-dependent dielectric breakdown, stress migration, and variable-amplitude thermal cycling. A new statistical reliability distribution is proposed for accurate characterization of components containing too few devices for an extreme value distribution to be appropriate. A hierarchical system-level survival lattice based Monte Carlo technique is used to estimate the temporal fault distributions of MPSoCs that use arbitrary static and dynamic reliability-enhancing redundancy schemes. Physical process variation, which may have a significant impact on MPSoC reliability, is considered in the model. The proposed modeling technique has 5% average error in mean time to failure and reduces simulation time by nearly 3 orders of magnitude relative to a non-hierarchical Monte Carlo technique.

关键词： Hierarchical systems

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