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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 854 条记录，以下是411-420 订阅

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FastFwd: An efficient hardware acceleration technique for trace-driven network-on-chip simulation 10

FastFwd: An efficient hardware acceleration technique for tr...

引用

Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Krishnaiah, Gummidipudi Silpa, B.V.N. Panda, Preeti Ranjan Kumar, Anshul Dept. of CSE IIT Delhi New Delhi India

ISBN: (纸本)9781605589053

We present an efficient emulation-based technique to accelerate architecture exploration of networks-on-chip (NoCs). The large design space of NoC along with its growing complexity that results in low simulation speeds on host machines have motivated the need for hardware accelerators for speeding up the simulation. For example, simulation of applications with real life problem sizes could take weeks on a host machine. FPGA acceleration is a promising strategy for speeding up NoC simulations by several orders of magnitude. However, it is required to simulate a few billion network transactions of the application during NoC exploration, and this could still take tens of minutes even with an FPGA-based emulator. With the increasing complexity of architectures and applications, reducing emulation time is a key concern. We propose a technique, FastFwd, to minimize emulation time by efficiently identifying and eliminating redundant cycles during a trace-based NoC simulation. We have studied the implications of the additional FPGA hardware required for implementing our technique. A naïve implementation could lead to poor scalability and increase the required DRAM bandwidth, both of which ultimately impact the emulation speed negatively. We propose a hierarchical controller architecture to resolve the scalability issue, and a compressed representation of traces for mitigating the increased DRAM bandwidth requirement. Our experiments with several benchmarks have shown that the FPGA emulation with our technique reduces the average emulation time by a factor of 2 when compared to a conventional emulation.

关键词： Network-on-chip

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Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications 10

Optimal synthesis of latency and throughput constrained pipe...

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Javaid, Haris He, Xin Ignjatovic, Aleksander Parameswaran, Sri School of Computer Science and Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781605589053

A streaming application, characterized by a kernel that can be broken down into independent tasks which can be executed in a pipelined fashion, inherently allows its implementation on a pipeline of Application Specific Instruction set Processors (ASIPs), called a pipelined MPSoC. The latency and throughput requirements of streaming applications put constraints on the design of such a pipelined MPSoC, where each ASIP has a number of available configurations differing by additional instructions, and instruction and data cache sizes. Thus, the design space of a pipelined MPSoC is all the possible combinations of ASIP configurations (design points). In this paper, a methodology is proposed to optimize the area of a pipelined MPSoC under a latency or a throughput constraint. The final design point is a set of ASIP configurations with one configuration for each ASIP. We proposed an Integer Linear Programming (ILP) based solution to the area optimization problem under a latency constraint, and an algorithm for optimization of pipelined MPSoC area under a throughput constraint. The proposed solutions were evaluated using four streaming applications: JPEG encoder;JPEG decoder;MP3 encoder;and H.264 decoder. The time to find the Pareto front of each pipelined MPSoC was less than 4 minutes where design spaces had up to 1016 design points, illustrating the applicability of our approach.

关键词： Throughput

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hardware-software codesign of fuzzy control systems using FPGAs

Hardware-software codesign of fuzzy control systems using FP...

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作者： Del Toro, E. Sánchez-Solano, S. Brox, M. Cabrera, A.J. CUJAE Ciudad de La Habana Cuba Sevilla Spain Dpto. Arquitectura de Computadores Electrónica Y Tecnología Electrónica Univ. Córdoba Spain Dpto. Automática Y Computación CUJAE Ciudad de La Habana Cuba

ISBN: (纸本)9789898425003

This paper describes a hardware/software codesign strategy for fuzzy control systems implementation using FPGAs. The main contribution of the paper consists of a methodology for joint development of hardware and software components intended for rapid and verifiable design of a fuzzy control system. The design flow combines specific tools for fuzzy inference systems included in the XFuzzy environment, simulation and modelling tools from Matlab and FPGA synthesis, and implementation tools provided by Xilinx. The advantages of this proposal are described in section 4 as it is used for the control system development of an autonomous vehicle.

关键词： Fuzzy control

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From ESL 2010 to ESL 2015 10

From ESL 2010 to ESL 2015

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Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Jeremiassen, Tor Martin, Grant Kogel, Tim Donlin, Adam Takach, Andres Chatha, Karam Texas Instruments United States Tensilica United States Synopsys United States Xilinx United States Mentor Graphics United States Arizona State University United States

ISBN: (纸本)9781605589053

In 2010, a wave of consolidation swept over the Electronic system Level (ESL) design industry. It brought ESL providers together with mainstream EDA houses and created opportunities for new ESL ventures. This paper contains short summaries of presentations in a special session focusing on the future of ESL. The session has two goals: the first is to present the state of the art in ESL tools and practice and, second, share a vision of the technical challenges that the next generation of ESL companies should address. The session includes a mix of perspectives from both ESL solution vendors and end-users and touches all all four ESL use cases: software virtual platforms, performance analysis, high level synthesis and verification.

关键词： High level synthesis

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An introduction to the systemC synthesis subset standard

An introduction to the SystemC synthesis subset standard

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作者： Coussy, Philippe Takach, Andres McNamara, Michael Meredith, Mike Université de Bretagne-Sud Rue de Saint Maude Lorient Cedex 56321 France Mentor Graphics 8005 SW Boeckman Rd. Wilsonville OR 97070 United States Cadence 2655 Seely Avenue San Jose CA 95134 United States Forte Design Systems 16150 NE 85th Street Redmond WA 98052 United States

ISBN: (纸本)9781605589053

High-level synthesis (HLS) offers the prospect of improving the productivity digital system design and the quality of the resulting implementations. Designing at higher levels of abstraction is a natural way for coping with system design complexity, for verifying earlier in the design process and for increasing design reuse [1][2][7]. © 2010 ACM.

关键词： High level synthesis

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hardware/software optimization of error detection implementation for real-time embedded systems

Hardware/software optimization of error detection implementa...

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作者： Lifa, Adrian Eles, Petru Peng, Zebo Izosimov, Viacheslav Linköping University Linköping Sweden Embedded Intelligent Solutions Linköping Sweden

ISBN: (纸本)9781605589053

This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant real-time distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when implemented in hardware, error detection is deployed on static reconfigurable FPGAs, while the second one considers partial dynamic reconfiguration capabilities of the FPGAs. © 2010 ACM.

关键词： Error detection

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From ESL 2010 to ESL 2015

From ESL 2010 to ESL 2015

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ISBN: (纸本)9781605589053

关键词： High level synthesis

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Towards a synthesis semantics for systemC channels

Towards a synthesis semantics for SystemC channels

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作者： Grüttner, Kim Kleen, Henning Oppenheimer, Frank Rettberg, Achim Nebel, Wolfgang OFFIS - Institute for Information Technology Escherweg 2 26121 Oldenburg Germany Carl Von Ossietzky University Oldenburg Faculty II - Department of Computer Science Ammerländer Heerstrasse 114-118 26111 Oldenburg Germany

ISBN: (纸本)9781605589053

In this paper we propose a synthesis semantics for systemC™ channels, which contribute to a clear separation between computation (algorithm) and communication, whereas communication related parts are modelled through either primitive or hierarchical channels. We present a synthesisable replacement for systemC primitive channels that allows deterministic access scheduling and user-constrained refinement for HW/HW and HW/SW communication. We demonstrate the feasibility of our approach through synthesis and exploration of a communication intensive packet switch design under consideration of different configurations and communication refinements. © 2010 ACM.

关键词： Semantics

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parSC: Synchronous parallel systemC simulation on multi-core host architectures

parSC: Synchronous parallel SystemC simulation on multi-core...

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作者： Schumacher, Christoph Leupers, Rainer Petras, Dietmar Hoffmann, Andreas Institute for Integrated Signal Processing Systems RWTH Aachen University Germany Synopsys Inc. Aachen Germany

ISBN: (纸本)9781605589053

Time-consuming cycle-accurate MPSoC simulation is often needed for debugging and verification. Its practicability is put at risk by the growing MPSoC complexity. This work presents a conservative synchronous parallel simulation approach along with a systemC framework to accelerate tightly-coupled MPSoC simulations on multi-core hosts. Key contribution is the implementation strategy, which utilizes techniques from the high-performance computing domain. Results show speed-ups of up to 4.4 on four host cores. © 2010 ACM.

关键词： system-on-chip

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From ESL 2010 to ESL 2015

From ESL 2010 to ESL 2015

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Tor Jeremiassen Grant Martin Tim Kogel Adam Donlin Andres Takach Karam Chatha Texas Instrumenits Inc. USA Synopsis Inc. Mentor Graphics Tensilica Xilinx Corporation Arizona State University USA

关键词： software system-on-a-chip Prototypes hardware Performance analysis Adaptation model Computer architecture

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