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共 854 条记录，以下是421-430 订阅

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Embedded market: Challenges and opportunities 10

Embedded market: Challenges and opportunities

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Vida Ilderem Integrated Platform Research Lab Intel Corporation Malaysia

ISBN: (纸本)9781605589053

There is a convergence trend in the computing, communication and consumer markets and with a forecast of an additional 1 billion connected computing users by 2015, it is of high value to provide a common experience between the devices. Intel's vision of Compute Continuum will enable the users to realize the potential of a seamless cross-device experience with more consistency and accessibility to their information. The convergence trend and the Compute Continuum make system-on-Chip [SoC] a key ingredient for the embedded markets. At Intel Labs, we are focusing on delivering differentiating technology solutions to enable our business partners to successfully capture their targeted market segments. We are working on a variety of research that will enable modular system architecture and silicon technology breakthroughs for rapid customization and integration facilitating faster time-to-market. Intel's vision along with some technology challenges and possible solutions will be highlighted.

关键词： system-on-a-chip Convergence Focusing Silicon Computer architecture Business hardware

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Improving platform-based system synthesis by satisfiability modulo theories solving

Improving platform-based system synthesis by satisfiability ...

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作者： Reimann, Felix Glaß, Michael Haubelt, Christian Eberl, Michael Teich, Jürgen University of Erlangen-Nuremberg Germany

ISBN: (纸本)9781605589053

Due to the ever increasing system complexity, deciding whether a given platform is sufficient to implement a set of applications under given constraints becomes a serious bottleneck in platform-based design. As a remedy, the work at hand proposes a novel automatic platform-based system synthesis procedure, inspired by techniques developed in the context of automatic system verification known as Satisfiability Modulo Theories. It tightly couples the computation of a feasible allocation and binding with nonfunctional constraint checking where, in contrast to existing approaches, not only linear constraints but even nonlinear constraints are supported. This allows to efficiently prove whether there exists a feasible implementation of a set of applications on the given platform with respect to both, functional and nonfunctional constraints. Moreover, an approach for early learning based on feasibility checking of partial implementations is proposed that can significantly improve the synthesis runtime, especially in case the selected platform imposes stringent constraints on the implementation. The effectiveness of this approach is shown for an automotive ECU network design that requires Modular Performance Analysis to ensure nonfunctional nonlinear timing constraints. © 2010 ACM.

关键词： Formal logic

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An elastic software cache with fast prefetching for motion compensation in video decoding

An elastic software cache with fast prefetching for motion c...

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作者： Chao, Ping Lin, Youn-Long Department of Computer Science National Tsing Hua University Hsin-Chu 30013 Taiwan

ISBN: (纸本)9781605589053

Real-time decoding of ultrahigh resolution video using multicore architectures is important for future embedded systems. However, memory bandwidth is still a bottleneck of system performance. Video coding performs irregular DRAM access resulting in very low and unstable efficiency. The conventional cache approach is insufficient because it reduces only the redundant accesses to data that has already been fetched during prior-macroblock decoding. We present an Elastic software Cache (ESC) for ultrahigh resolution video decoding on Scratchpad Memory (SPM)-based systems. Utilizing access region analysis, our latency-optimized prefetching scheme rearranges accesses to minimize both data redundancy and DRAM access latency. Compared to the conventional cache approach, our scheme requires only 4.6 Kbytes of SPM space but it can save up to 25% of memory access cycles resulting in both higher performance and lower power. © 2010 ACM.

关键词： Decoding

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Embedded tutorial — Compilation techniques for CGRAs: Exploring all parallelization approaches

Embedded tutorial — Compilation techniques for CGRAs: Explo...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Tom Vander Aa Praveen Raghavan Scott Mahlke Bjorn De Sutter Aviral Shrivastava Frank Hannig Imec Leuven Belgium University of Michigan Ghent University Arizona State University University of Erlangen-Nuremberg

Coarse-Grained Reconfigurable Array (CGRA) processors accelerate inner loops of applications by exploiting instructionlevel parallelism (ILP) and in some cases also data-level and task-level parallelism (DLP & TLP). The aim of this tutorial is to give insight in CGRA architectures and their compilation techniques to exploit parallelism. These topics will be covered: · Polymorphic pipeline arrays, expanding coarse-grained arrays beyond innermost loops (Scott Mahlke, University of Michigan) · Code-generation for coarse-grained arrays: flexibility and programmer productivity (Bjorn De Sutter, Ghent University) · Memory-aware compilation techniques for CGRAs (Aviral Shrivastava, Arizona State University) · Retargetable Mapping of Loop Programs on Coarse-grained Reconfigurable Arrays (Frank Hannig, University of Erlangen-Nuremberg).

关键词： Arrays Parallel processing Pipelines Productivity software Streaming media

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Embedded systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

ISBN: (纸本)9781605584706

The proceedings contain 46 papers. The topics discussed include: concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design;a time-predictable system initialization design for huge-capacity flash-memory storage systems;deterministic service guarantees for NAND flash using partial block cleaning;static analysis of processor stall cycle aggregation;application specific non-volatile primary memory for embedded systems;scratchpad allocation for concurrent embedded software;hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits;a performance-oriented hardware/software partitioning for datapath applications;traversal caches: a first step towards FPGA acceleration of pointer-based data structures;and distributed and low-power synchronization architecture for embedded multiprocessors.

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Exploring models of computation with Ptolemy II

Exploring models of computation with Ptolemy II

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Christopher Brooks Edward A. Lee Stavros Tripakis EECS Department University of California Berkeley Berkeley CA USA

The Ptolemy project studies modeling, simulation, and design of concurrent, real-time, embedded systems. The focus is on assembly of concurrent components. The key underlying principle in the project is the use of well-defined models of computation that govern the interaction between components. A major problem area being addressed is the use of heterogeneous mixtures of models of computation. Ptolemy II takes a component view of design, in that models are constructed as a set of interacting components. A model of computation governs the semantics of the interaction, and thus imposes an execution-time discipline. Ptolemy II has implementations of many models of computation including Synchronous Data Flow, Kahn Process Networks, Discrete Event, Continuous Time, Synchronous/Reactive and Modal Models This hands-on tutorial explores how these models of computation are implemented in Ptolemy II and how to create new models of computation such as a "non-dogmatic" Process Networks example and a left-to-right execution policy example.

关键词： Computational modeling Object oriented modeling Semantics Data models Tutorials software Real time systems

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FEMU: A firmware-based emulation framework for SoC verification

FEMU: A firmware-based emulation framework for SoC verificat...

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作者： Li, Hao Tong, Dong Huang, Kan Cheng, Xu Microprocessor Research and Development Center Peking University Beijing China

ISBN: (纸本)9781605589053

Full-system emulation on FPGA(Field-Programmable Gate Array) with real-world workloads can enhance the confidence of SoC(system-on-Chip) design. However, since FPGA emulation requires complete implementation of key modules and provides weak visibility, it is time-consuming. This paper proposes FEMU, a hybrid firmware/hardware emulation framework for SoC verification. The core of FEMU is implemented by transplanting QEMU, a full-system emulator, from OS level to BIOS level, so we can directly emulate devices upon hardware. Moreover, FEMU provides programming interfaces to simplify device modeling in firmware. Based on an auxiliary set of hardware modules, FEMU allows hybrid full-system emulation with the combination of real hardware and emulated firmware model. Therefore, FEMU can facilitate full-system emulation in three aspects. First, FEMU enables full-system emulation with the minimum hardware implementation, so the DUT (Design Under Test) module can be verified under target application as early as possible. Second, by comparing the execution traces generated using real hardware and emulated firmware model, respectively, FEMU helps locate and fix bugs occurred in the full-system emulation. Third, by replacing un-verified hardware modules with emulated firmware models, FEMU helps isolating design issues in multiple modules. In a practical SoC project, FEMU helped us identify several design issues in full-system emulation. In addition, the evaluation results show that the emulation speed of FEMU is comparable with QEMU after transplantation. © 2010 ACM.

关键词： system-on-chip

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Accurate online power estimation and automatic battery behavior based power model generation for smartphones

Accurate online power estimation and automatic battery behav...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Lide Zhang Birjodh Tiwana Robert P. Dick Zhiyun Qian Z. Morley Mao Zhaoguang Wang Lei Yang TEECS Department University of Michigan Ann Arbor MI USA Google Inc. Mountain View CA USA

This paper describes PowerBooter, an automated power model construction technique that uses built-in battery voltage sensors and knowledge of battery discharge behavior to monitor power consumption while explicitly controlling the power management and activity states of individual components. It requires no external measurement equipment. We also describe PowerTutor, a component power management and activity state introspection based tool that uses the model generated by PowerBooter for online power estimation. PowerBooter is intended to make it quick and easy for application developers and end users to generate power models for new smartphone variants, which each have different power consumption properties and therefore require different power models. PowerTutor is intended to ease the design and selection of power efficient software for embedded systems. Combined, PowerBooter and PowerTutor have the goal of opening power modeling and analysis for more smartphone variants and their users.

关键词： Cameras Ground penetrating radar Brightness Bluetooth Monitoring Global Positioning system Batteries

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A holistic approach to Network-on-Chip synthesis

A holistic approach to Network-on-Chip synthesis

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作者： Leary, Glenn Chatha, Karam S. Arizona State University Department of CSE P.O. Box 875406 Tempe AZ 85287-5406 United States

ISBN: (纸本)9781605589053

Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor system-on-Chip architectures. synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints. © 2010 ACM.

关键词： Network-on-chip

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Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming

Automatic parallelization of embedded software using hierarc...

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作者： Cordes, Daniel Marwedel, Peter Mallik, Arindam Informatik Centrum Dortmund Joseph-von-Fraunhofer-Str. 20 Dortmund Germany Imec Belgium Kapeldreef 75 Leuven Belgium

ISBN: (纸本)9781605589053

The last years have shown that there is no way to disregard the advantages provided by multiprocessor system-on-Chip (MPSoC) architectures in the embedded systems domain. Using multiple cores in a single system enables to close the gap between energy consumption, problems concerning heat dissipation, and computational power. Nevertheless, these benefits do not come for free. New challenges arise, if existing applications have to be ported to these multiprocessor platforms. One of the most ambitious tasks is to extract efficient parallelism from these existing sequential applications. Hence, many parallelization tools have been developed, most of them are extracting as much parallelism as possible, which is in general not the best choice for embedded systems with their limitations in hardware and software support. In contrast to previous approaches, we present a new automatic parallelization tool, tailored to the particular requirements of the resource constrained embedded systems. Therefore, this paper presents an algorithm which automatically steers the granularity of the generated tasks, with respect to architectural requirements and the overall execution time reduction. For this purpose, we exploit hierarchical task graphs to simplify a new integer linear programming based approach in order to split up sequential programs in an efficient way. Results on real-life benchmarks have shown that the presented approach is able to speed sequential applications up by a factor of up to 3.7 on a four core MPSoC architecture. © 2010 ACM.

关键词： Embedded systems

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