This paper presents an investigation into the possibility of using a regular concurrent programming language for modeling and implementing digital circuits. Some of the reasons for using an existing language include t...
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This paper presents an investigation into the possibility of using a regular concurrent programming language for modeling and implementing digital circuits. Some of the reasons for using an existing language include the ability to use existing compilers and analysis tools for circuit design and verification. Another important reason is the ever increasing need to model complete systems that comprise interacting software and hardware in a single framework which facilitates easier migration of sub-components between hardware and software implementations compared to multi-model approaches. To this end we present the design of the Kiwi system which models digital circuits with concurrent programs using a standard library in C# for multi-threaded programming. Kiwi models can be executed using a regular C# compiler. Also, the compiled bytecode can be automatically converted into circuits using our Kiwi hardwaresynthesissystem.
We present an efficient emulation-based technique to accelerate architecture exploration of networks-on-chip (NoCs). The large design space of NoC along with its growing complexity that results in low simulation speed...
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The reliability of multi-processor systems-on-chip (MPSoCs) is affected by several inter-dependent system-level and physical effects. Accurate and fast reliability modeling is a primary challenge in the design and opt...
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A streaming application, characterized by a kernel that can be broken down into independent tasks which can be executed in a pipelined fashion, inherently allows its implementation on a pipeline of Application Specifi...
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Low-power embedded system design has become extremely important in the most recent years. To fulfill system-level design requirements and time-to-market constraints, a power-driven methodology is essential during embe...
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ISBN:
(纸本)9780769536422
Low-power embedded system design has become extremely important in the most recent years. To fulfill system-level design requirements and time-to-market constraints, a power-driven methodology is essential during embedded system design. The aim of this paper is to introduce accurate and efficient power metrics included in a hardware/software (HW/SW) co-design environment to show the system-level partitioning and design. In order to verify the design effectiveness of hardware/software co-design synthesis, we consider the digital power dissipation methodology and its power reduction techniques. To maximize the performance of system, we developed hierarchical design technique and co-design synthesis for power efficient HW/SW co-design process. In the end, we provided simulation results for single circuit with new design vs. circuit integration with hierarchical power efficiency system (HPES), multiple circuits with new design vs. circuit integration with HPES, new design and no load vs. circuit integration with HPES, new design with load vs. circuit integration with HPES.
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