The complexity of hardware design methodologies represents a significant difficulty for non hardware focused scientists working on CNN-based applications. An emerging generation of Electronic system Level (ESL) design...
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In this paper, an FPGA-based design and implementation of a high-performance video processing platform (VPP) is presented. A hardware/softwarecodesignsystem is proposed on Xilinx Virtex II Pro FPGA to realize comple...
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In this paper, an FPGA-based design and implementation of a high-performance video processing platform (VPP) is presented. A hardware/softwarecodesignsystem is proposed on Xilinx Virtex II Pro FPGA to realize complex algorithms for real-time image and video processing. This paper presents the framework of the VPP, discusses the architectural building blocks and FPGA synthesis results. Each hardware (custom accelerator blocks) and software (code running on an embedded CPU core) component is described comprehensively, laying the foundation for an adaptable and modular embedded system. As a case study, a real-time motion detection algorithm is implemented, demonstrating the feasibility of the proposed platform. Additional hardware accelerators can be easily plugged-in to the system for desired processing engines. VPP can be a robust, cost-effective solution for a broad range of multimedia applications including broadcasting and streaming video, video on-demand, video encoding/decoding, surveillance, detection and recognition.
The proceeding contains 47 papers. The topics discussed include: temperature-aware processor frequency assignment for MPSoCs using convex optimization;three-dimensional multiprocessor system-on-chip thermal optimizati...
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ISBN:
(纸本)9781595938244
The proceeding contains 47 papers. The topics discussed include: temperature-aware processor frequency assignment for MPSoCs using convex optimization;three-dimensional multiprocessor system-on-chip thermal optimization;complexity challenges towards 4th generation communication solutions;locality optimization in wireless applications;a code-generator generator for multi-output instructions;influence of procedure cloning on WCET prediction;compile-time decided instruction cache locking using worst-case execution paths;predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules;incremental run-time application mapping for homogenous NoCs with multiple voltage levels;a data protection unit for NoC-based architectures;improved response time analysis of tasks scheduled under preemptive round-robin;probabilistic performance risk analysis at system-level;and performance modeling for early analysis of multi-core systems.
We conducted a study of citations of papers published between 1996 and 2006 in the CODES and ISSS conferences, representing the hardware/softwarecodesign and systemsynthesis community. Citations, meaning non-self-ci...
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ISBN:
(纸本)9781605584706
We conducted a study of citations of papers published between 1996 and 2006 in the CODES and ISSS conferences, representing the hardware/softwarecodesign and systemsynthesis community. Citations, meaning non-self-citations only, were considered from all papers known to Google Scholar, as well as only from subsequent CODES/ISSS papers. We list the most-cited CODES/ISSS papers of each year, summarizing their topics, and discussing common features of those papers. For comparison purposes, we also measured citations for the computer architecture community's ISCA and MICRO conferences, and for the field-programmable gate array community's FPGA and FCCM conferences. We point out several interesting differences among the citation patterns of the three communities. Copyright 2008 ACM.
This paper presents a systemsynthesis approach for dependable embedded systems. The proposed approach significantly extends previous work by automatically inserting fault detection and fault toleration mechanisms int...
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ISBN:
(纸本)9781605584706
This paper presents a systemsynthesis approach for dependable embedded systems. The proposed approach significantly extends previous work by automatically inserting fault detection and fault toleration mechanisms into an implementation. The main contributions of this paper are 1) a dependability-aware systemsynthesis approach that automatically performs a redundant task binding and placement of voting structures to increase both, reliability and safety, respectively, 2) an efficient dependability analysis approach to evaluate lifetime reliability and safety, and 3) results from synthesizing a Motion-JPEG decoder for an FPGA platform using the proposed systemsynthesis approach. As a result, a set of high-quality solutions of the decoder with maximized reliability, safety, performance, and simultaneously minimized resource requirements is achieved. Copyright 2008 ACM.
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