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You can catch more bugs with transaction level honey 08

You can catch more bugs with transaction level honey

引用

Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Abramovici, Miron Goossens, Kees Vermeulen, Bart Greenbaum, Jack Stollon, Neal Donlin, Adam DAFCA NXP Greenhills Software United States HDL Dynamics Xilinx Research

ISBN: (纸本)9781605584706

In this special session we explore holistic approaches to hardware/software debug that use or integrate transaction level models (TLMs). We present several TLM-based approaches to system-level diagnostics, ranging from use of most popular transaction level modeling languages through to hybrid technologies that combine TLMs with other well known diagnostic tools like in-silicon trace logic. Copyright 2008 ACM.

关键词： Modeling languages

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HW/SW auto-coupling for fast IP integration in SoC designs

HW/SW auto-coupling for fast IP integration in SoC designs

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5th international conference on Embedded software and systems

作者： Hwang, Yin-Tsung Chen, Jun-Yen Chiu, Jun-Jieh Natl Chung Hsing Univ Dept Elect Engn Taichung 40201 Taiwan

ISBN: (纸本)9780769532875

IP intergration in SoC nowadays contains two design aspects, i.e. hardware interface and software driver. The hardware interface supports necessary signal mapping, protocol translation and data buffering so that an IP can adapt to various system architectures. The software driver provides IP access controls from the software domain in the presence of operating system. The automation of both design processes in a coupling manner is addressed in this paper. We first outline the methodology of automatic interface synthesis and elaborate on the topics of signal mapping, protocol conversion and interface template architecture. We next present the framework of a baseline driver generator and detail the generation schemes of basic file operations and other functions and driver settings. Both tools are linked to form a HW/SW auto-coupling design suite, which features minimum user knowledge toward the hardware and OS details in usage. Some design examples on the interface synthesis tool and an JPEG codec HW/SW codesign example on the integrated design suite are provided to prove the effectiveness of the proposed system.

关键词： system-on-chip

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hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits 08

Hardware/software partitioning of floating point software ap...

引用

Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Saldanha, Lance Lysecky, Roman Department of Electrical and Computer Engineering University of Arizona United States

ISBN: (纸本)9781605584706

While hardware/software partitioning has been shown to provide significant performance gains, most hardware/software partitioning approaches are limited to partitioning computational kernels utilizing integers or fixed point implementations. software developers often initially develop an application using built-in floating point representations and later convert the application to a fixed point representation - a potentially time consuming process. In this paper, we present a hardware/software partitioning approach for floating point applications that eliminates the need for developers to rewrite software applications for fixed point implementations. Instead, the proposed approach incorporates efficient, configurable floating point to fixed point and fixed point to floating point hardware converters at the boundary between the hardware coprocessors and memory. This effectively separates the system into a floating point domain consisting of the microprocessor and memory subsystem and a fixed point domain consisting of the partitioned hardware coprocessors, thereby providing an efficient and rapid method for implementing fixed point hardware coprocessors. Copyright 2008 ACM.

关键词： Coprocessor

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A performance-oriented hardware/software partitioning for datapath applications 08

A performance-oriented hardware/software partitioning for da...

引用

Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Frigerio, Laura Salice, Fabio Dip. di Elettronica e Informazione Politecnico di Milano Piazza Leonardo da Vinci Milano Italy

ISBN: (纸本)9781605584706

This article proposes a hardware/software partitioning method targeted to performance-constrained systems for datapath applications. Exploiting a platform based design, a Timed Petri Net formalism is proposed to represent the mapping of the application onto the platform, allowing to statically extract performance estimations in early phases of the design process and without the need of expensive simulations. The mapping process is generalized in order to allow an automatic exploration of the solution space, that identifies the best performance/area configurations among several application-architecture combinations. The method is evaluated implementing a typical datapath performance constrained system, i.e. a packet processing application. Copyright 2008 ACM.

关键词： Mapping

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Specification and OS-based implementation of self-adaptive, hardware/software embedded systems 08

Specification and OS-based implementation of self-adaptive, ...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Eustache, Yvan Diguet, Jean-Philippe Université Européenne de Bretagne UBS LabSTICC Lorient France

ISBN: (纸本)9781605584706

This paper presents our solution for specifying and imple-menting self-adaptivness within an OS-based and reconfig-urable embedded system according to objectives such as qual-ity of service (QoS), performance or power consumption. More precisely, we detail our approach to separate, at runtime, application-specific decisions and hardware/software imple-mentation decisions at system level. The first ones are re-lated to the control of the efficiency of applications, they are specified in Local Configuration Managers (LCM) based on the knowledge of application engineers. The second ones are generic and address the choice between various hardware and software implementations according to observations of the gap between online measurements and objectives set by the user, these decisions are implemented in the Global Con-figuration Manager (GCM) as an adaptive close-loop model. We have designed a video tracking application on an FPGA to demonstrate the effectiveness of our solution, results are given for a system built around a NIOS soft-core with μCOS II RTOS and new services for managing hardware and soft-ware tasks transparently. Copyright 2008 ACM.

关键词： Embedded systems

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Simulation and embedded software development for anton, a parallel machine with heterogeneous multicore ASICs 08

Simulation and embedded software development for anton, a pa...

引用

Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Grossman, J.P. Young, Cliff Bank, Joseph A. Mackenzie, Kenneth Lerardi, Douglas J. Salmon, John K. Dror, Ron O. Shaw, David E. D. E. Shaw Research New York NY 10036 United States

ISBN: (纸本)9781605584706

Anton, a special-purpose parallel machine currently under construction, is the result of a significant hardware-software codesign effort that relied heavily on an architectural simulator. One of this simulator's many important roles is to support the development of embedded software (software that runs on Anton's ASICs), which is challenging for several reasons. First, the Anton ASIC is a heterogeneous multicore system-on-a-chip, with three types of embedded cores tightly coupled to special-purpose hardware units. Second, a standard 512-ASIC configuration contains a total of 6,656 distinct embedded cores, all of which must be explicitly modeled within the simulator. Third, a portion of the embedded software is dynamically generated at simulation time. This paper discusses the various ways in which the Anton simulator addresses these challenges. We use a hardware abstraction layer that allows embedded software source code to be compiled without modification for either the simulation host or the hardware target. We report on the effectiveness of embedding golden-model testbenches within the simulator to verify embedded software as it runs. We also describe our hardware-software co-simulation strategy for dynamically generated embedded software. Finally, we use a methodology that we refer to as concurrent mixed-level simulation to model embedded cores within massively parallel systems. These techniques allow the Anton simulator to serve as an efficient platform for embedded software development. Copyright 2008 ACM.

关键词： Abstracting

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Slack analysis in the system design loop 08

Slack analysis in the system design loop

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Venkataramani, Girish Goldstein, Seth C. ECE Department Carnegie Mellon University Pittsburgh PA United States School of Computer Science Carnegie Mellon University Pittsburgh PA United States

ISBN: (纸本)9781605584706

We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by substituting, in the design the loop, the time-consuming simulation step with a fast timing update routine. As a result, we can significantly reduce the design time from on the order of hours/days to the order of seconds/minutes. The update algorithm is defined on the Transaction Level Model (TLM) and can be used by any design flow that invokes TLM-based optimizations. This algorithm has linear-time complexity in the program size and experimental results indicate that any loss of accuracy due to this technique is negligible (

关键词： systems analysis

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A time-predictable system initialization design for huge-capacity flash-memory storage systems 08

A time-predictable system initialization design for huge-cap...

引用

Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Wu, Chin-Hsien Department of Electronic Engineering National Taiwan University of Science and Technology Taipei Taiwan

ISBN: (纸本)9781605584706

The capacity of flash-memory storage systems grows at a speed similar to many other storage systems. In order to properly manage the product cost, vendors face serious challenges in system designs. How to provide an expected system initialization time for huge-capacity flash-memory storage systems has become an important research topic. In this paper, a time-predictable system initialization design is proposed for huge-capacity flash-memory storage systems. The objective of the design is to provide an expected system initialization time based on a coarse-grained flash translation layer. The time-predictable analysis of the design is provided to discuss the relation between the size of main memory and the system initialization time. The system initialization time can be also estimated and predicted by the time-predictable analysis. Copyright 2008 ACM.

关键词： Flash memory

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Model checking systemC designs using timed automata 08

Model checking SystemC designs using timed automata

引用

Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Herber, Paula Fellmuth, Joachim Glesner, Sabine Software Engineering for Embedded Systems Group Technical University of Berlin Germany

ISBN: (纸本)9781605584706

systemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify systemC designs. In this paper, we present an approach to overcome this problem by defining the semantics of systemC by a mapping from systemC designs into the well-defined semantics of UPPAAL timed automata. The informally defined behavior and the structure of systemC designs are completely preserved in the generated UPPAAL models. The resulting UPPAAL models allow us to use the UPPAAL model checker and the UPPAAL tool suite, including simulation and visualization tools. The model checker can be used to verify important properties such as liveness, deadlock freedom or compliance with timing constraints. We have implemented the presented transformation, applied it to two examples and verified liveness, safety and timing properties by model checking, thus showing the applicability of our approach in practice. Copyright 2008 ACM.

关键词： Semantics

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Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design 08

Concurrency emulation and analysis of parallel applications ...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Beltrame, Giovanni Fossati, Luca Sciuto, Donatella European Space Agency Keplerlaan 1 Noordwijk Netherlands Politecnico di Milano Piazza Leonardo da Vinci Milano Italy

ISBN: (纸本)9781605584706

This paper presents a novel technique for the modeling and the simulation of parallel applications for Multi-Processor systems-on-Chip (MPSoCs). This technique consists of an application-transparent emulation of OS primitives, includ-ing task creation, scheduling, synchronization etc.;this emu-lation guarantees compatibility with any program compiled against the standard POSIX library, independently of the target OS. This methodology can be used to perform initial HW/SW partitioning and concurrent engineering of a given application, as it allows any software routine to be trans-parently emulated with systemC modules. The proposed approach has been verified on a large set of multi-threaded benchmarks, with both POSIX Threads and OpenMP pro-gramming styles. Results show that our methodology en-ables (a) fast simulation of POSIX applications, (b) accurate analysis of multi-threaded applications, and (c) co-design and fast preliminary hardware-software partitioning. This work has been partially supported by the European HiPEAC network of excellence. Copyright 2008 ACM.

关键词： system-on-chip

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