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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 852 条记录，以下是41-50 订阅

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Conflict analysis in multiprocess synthesis for optimized system integration 05

Conflict analysis in multiprocess synthesis for optimized sy...

引用

international conference on hardware/software codesign and system synthesis

作者： Bringmann, O Siebenborn, A Rosenstiel, W FZI Forschungszentrum Informat D-76131 Karlsruhe Germany

ISBN: (纸本)1595931619

This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing architectural synthesis approaches in order to apply global optimization techniques across process bounds for shared system resources (e.g. memories, busses, global ALUs) during scheduling and binding. This allows an area efficient implementation of un-timed or cycle-fixed multiprocess specifications at RT or algorithmic level of abstraction. Furthermore, this approach supports environment-oriented synthesis for optimized module integration by scheduling accesses to global resources with respect to the access schedules of other modules communicating to the same global resources. As a result, dynamic access conflicts can be avoided by construction, and hence, there is no need for dynamic arbitration of bus and memory accesses with potentially unpredictable timing behavior.

关键词： behavioral synthesis system level design systems-on-chip scheduling binding concurrent systems

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Special Session Paper: An Efficient hardware Design for Cerebellar Models using Approximate Circuits 12

Special Session Paper: An Efficient Hardware Design for Cere...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Jiang, Honglan Liu, Leibo Han, Jie Univ Alberta Edmonton AB Canada Tsinghua Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781450351850

The superior controllability of the cerebellum has motivated extensive interest in the development of computational cerebellar models. Many models have been applied to the motor control and image stabilization in robots. Often computationally complex, cerebellar models have rarely been implemented in dedicated hardware. Here, we propose an efficient hardware design for cerebellar models using approximate circuits with a small area and a low power. Leveraging the inherent error tolerance in the cerebellum, approximate adders and multipliers are carefully evaluated for implementations in an adaptive filter based cerebellar model to achieve a good tradeoff in accuracy and hardware usage. A saccade system, whose vestibulo-ocular reflex (VOR) is controlled by the cerebellum, is simulated to show the applicability and effectiveness of the proposed design. Simulation results show that the approximate cerebellar circuit achieves a similar accuracy as an exact implementation, but it saves area by 29.7% and power by 37.3%.

关键词： Cerebellar model approximate circuits multiplier adder

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Work-in-Progress: Lark: A Learned Secondary Index Toward LSM-tree for Resource-Constrained Embedded Storage systems

Work-in-Progress: Lark: A Learned Secondary Index Toward LSM...

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ACM/IEEE international conference on hardware/software codesign and system synthesis part of the Embedded systems Week (ESWEEK)

作者： Yuan, Jianan Liu, Huan Wu, Shangyu Lin, Yiquan Wang, Tiantian Ma, Chenlin Mao, Rui Wang, Yi Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen Peoples R China City Univ Hong Kong Memory Syst & IoT Lab Hong Kong Peoples R China

ISBN: (数字)9781665472944

ISBN: (纸本)9781665472944

LSM-tree-based key-value stores are popular in embedded storage systems. With the growing demands of data analysis, the secondary index is created to support non-primary-key lookups. However, the lookup efficiency and space consumption of secondary index remain for further optimization. Inspired by the learned index, this paper presents Lark, a learned secondary index toward LSM-tree for resource-constrained embedded storage systems. Lark employs machine learning to speed up the non-primary-key queries and compress secondary indexes. Our preliminary evaluations show that, in comparison with traditional secondary index schemes, Lark achieves better lookup performance with less space consumption.

关键词： Secondary index LSM-tree machine learning

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Extending the systemC synthesis subset by object-oriented features

Extending the SystemC synthesis subset by object-oriented fe...

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Grimpe, E Oppenheimer, F OFFIS Res Inst D-26121 Oldenburg Germany

ISBN: (纸本)1581137427

In this article we present an approach to object-oriented hardware design and synthesis based on systemC. We will give an introduction to an extended systemC synthesis subset which we propose, and;in particular, its object-oriented features. We will also briefly outline our basic synthesis concepts for object-oriented hardware specifications. Finally we will present some examples for the application of the extended synthesis subset, which are directly processable by a first synthesis tool prototype which we have developed for this purpose.

关键词： systemC C/C plus plus based design hardware description language hardware synthesis system level design object-orientation high-level synthesis

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Work-in-Progress: Heterogeneous Redundancy to Address Performance and Cost in Multi-core SIMT 12

Work-in-Progress: Heterogeneous Redundancy to Address Perfor...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Naghashi, M. Mozafari, S. H. Hessabi, S. Sharif Univ Technol Tehran Iran McGill Univ Montreal PQ Canada

ISBN: (纸本)9781450351850

As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. In this work, we investigate adding heterogeneous hot redundancy (i.e., the architecture of redundant hot cores is diferent from the baseline cores) to improve the cost and performance of multicore single-instruction, multiple-thread (SIMT) architectures. We propose to utilize x86 out of order (OoO) cores as redundancy in SIMT processors. In this case, dice with unused functional redundancies can beneit from two types of processing cores (OoO and SM).

关键词： Manufacturability system-level design redundancy

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Current flattening in software and hardware for security applications

Current flattening in software and hardware for security app...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Muresan, R Gebotys, C Univ Guelph Guelph ON N1G 2W1 Canada

ISBN: (纸本)1581139373

This paper presents a new current flattening technique applicable in software and hardware. This technique is important in embedded cryptosystems since power analysis attacks (that make use of the current variation dependency on data and program) compromise the security of the system. The technique flattens the current internally by exploiting current consumption differences at the instruction level. Code transformations supporting current variation reductions due to program dependencies are presented. Also, a new real-time hardware architecture capable of reducing the current to data and program dependencies is proposed. Measured and simulated current waveforms of cryptographic software are presented in support of these techniques.

关键词： current flattening power analysis attacks hardware architecture

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CoChrono: A Unified hardware/software Performance Analysis Tool for SoC-FPGA codesign 22

CoChrono: A Unified Hardware/Software Performance Analysis T...

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22nd IEEE Interregional NEWCAS conference (NEWCAS)

作者： Portas, Fabien Bois, Guy Savaria, Yvon Polytech Montreal Comp Engn Dept Montreal PQ Canada Polytech Montreal Elect Engn Dept Montreal PQ Canada

ISBN: (纸本)9798350361766;9798350361759

High-level embedded system design tools are making the design of complex SoC-FPGA systems more accessible than ever before. However, this comes at the cost of more opacity as implementations result from heavy transformations made by high-level synthesis tools, while there is a lack of complete suitable performance analysis tools for the resulting implementations. This paper proposes a unified application programmer interface and methodology that enables the extraction of time points to instrument performance metrics for hardware/software co-simulation and monitoring the SoC-FPGA execution. The proposed tool, called CoChrono, leverages high-level synthesis and code generation to access metrics similarly in software and hardware C++ code. The tool's features and low overhead are demonstrated with a practical application of architecture exploration and simulation model validation. Compared to instruments manually inserted using existing tools, CoChrono significantly reduces the effort required to validate complex timing constraints in hardware/software systems.

关键词： monitoring instrumentation SoC-FPGA HLS performance metrics HW/SW codesign system-level design

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Automated Firmware Testing using Firmware-hardware Interaction Patterns 14

Automated Firmware Testing using Firmware-Hardware Interacti...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Ahn, Sunha Malik, Sharad Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)9781450330510

Firmware is low-level software which can directly access hardware and is often shipped with the hardware platform. This component of the system is increasing in scale and importance, and thus firmware validation is a critical part of system validation. Firmware validation relies on the interacting hardware components which are usually not available until the late design stages. This is generally addressed through co-simulating C/C++ based firmware code and HDL hardware models (including systemC). However, this tends to be slow, and is further exacerbated by the large number of possible interleavings between the concurrent firmware and hardware threads. Typically, in the co-simulation, the scheduler, such as the systemC scheduler, will only explore a single, or at best a small number of possible firmware-hardware interleavings and thus may miss critical bugs. In this paper we present an alternative approach to firmware validation that is based on automatically generating a test-set for the firmware with the goal of complete path coverage while considering its interactions with hardware and other firmware threads. It uses a service-function based Transaction Level Model (TLM) which has been used in the past for firmware hardware codesign. The test generation is based on concolic testing which has been used successfully in software test generation. However, existing concolic testing tools are used for test-generation of sequential code, and cannot directly consider the interaction of other hardware/firmware threads with the target firmware thread during test generation. We address this limitation by exploiting specific interaction patterns between the firmware and hardware threads that can be analyzed from the TLM. We show how these patterns, along with the firmware and hardware threads are used to automatically generate a sequential program that is test-equivalent to the target firmware transaction and that can be used with a standard sequential program concolic test

关键词： firmware hardware-software codesign multi-threading program testing program verification C++ based firmware code Frama-C HDL hardware models KLEE Linux device driver code QEMU emulated hardware code systemC scheduler TLM automated firmware testing concolic testing tools concurrent firmware firmware benchmarks firmware transaction firmware validation firmware-hardware codesign firmware-hardware interaction patterns firmware-hardware interleavings hardware components hardware-firmware thread interaction low-level software multithreaded interactions sequential code test-generation service-function based transaction level model software test generation standard sequential program concolic test generator static code analyzer system validation Benchmark testing Computer bugs Generators hardware Microprogramming software Firmware Computer hardware Trefoil Microprogramming Benchmark testing Multithreading Test generation hardware/software co-design program testing program verification dynamos LOW LEVEL computer software Transmission line measurements system validation

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Generating Situation Awareness in Cyber-Physical systems: Creation and Exchange of Situational Information 14

Generating Situation Awareness in Cyber-Physical Systems: Cr...

引用

international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Preden, Jurgo Tallinn Univ Technol Res Lab Proact Technol Tallinn Estonia

ISBN: (纸本)9781450330510

Cyber-physical systems depend on good situation awareness in order to cope with the changes of the physical world and in the configuration of the system to fulfill their goal functions. Being aware of the situation in the physical world enables a cyber-physical system to adapt its behaviour according to the actual state of the world as perceived by the cyber-physical system. Understanding the situation of the cyber-physical system itself enables adaptation of the behaviour of the system according to the current capabilities and state of the system, e.g., providing less features or features with limited functionality in case some of the system components are not functional. In order to build resilient cyber-physical systems we need to build systems that are able to consider both of these aspects in their operation.

关键词： situation awareness cyber physical system

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Work-in-Progress: A Fast Online Sequential Learning Accelerator for IoT Network Intrusion Detection 12

Work-in-Progress: A Fast Online Sequential Learning Accelera...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Huang, Hantao Khalid, Rai Suleman Liu, Wenye Yu, Hao Nanyang Technol Univ Sch Elect & Elect Engn Singapore Singapore

ISBN: (纸本)9781450351850

Deployment of IoT devices for smart buildings and homes will offer a high level of comfortability with increased energy efficiency;but can also introduce potential cyber-attacks such as network intrusions via linked IoT devices. Due to the low-power and low-latency requirement to secure IoT network, traditional software based security system is not applicable. Instead, an embedded hardware-accelerator based data analytics is more preferred for network intrusion detection. In this paper, we propose an online sequential machine learning hardware accelerator to perform real-time network intrusion detection. A single hidden layer feedforward neural network based learning algorithm is developed with a least-squares solver realized on hardware. Experimental results on a single FPGA achieve a bandwidth of 409.6 Gbps with fast yet low-power network intrusion detection based on a number of benchmarks.

关键词： Intrusion detection hardware Training Field programmable gate arrays Benchmark testing Telecommunication traffic Computer architecture

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