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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

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Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC

Simultaneous synthesis of buses, data mapping and memory all...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Meyer, Brett H. Thomas, Donald E. Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA 15213 United States

ISBN: (纸本)9781595938244

Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the target applications, these systems will also have custom memory and bus architectures. Because of performance and cost constraints, these systems must be carefully designed to balance system partitioning and resource sharing. The sheer size of the design space requires that tools be able to do this balancing. We have developed an augmented simulated annealing synthesis tool that uses system performance and layout evaluation to drive simultaneous data mapping, memory allocation and bus synthesis. Performing these optimizations at the same time, our tool is able to explore a larger design space and take advantage of cost-saving resource sharing unavailable to previous approaches that allocate memories before synthesizing buses. This results in 20% cost reduction for high-performance designs as well as 27% for low-cost designs in comparison with an approach that performs memory allocation and data mapping separately from bus synthesis. Copyright 2007 ACM.

关键词： Multiprocessing systems

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Embedded software development on top of transaction-level models

Embedded software development on top of transaction-level mo...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Klingauf, Wolfgang Günzel, Robert Schröder, Christian Technical University of Braunschweig Dept. E.I.S. Mühlenpfordtstr. 23 38106 Braunschweig Germany

ISBN: (纸本)9781595938244

Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write operations via a TLM interconnect. SW developers have to implement platform-specific communication procedures and handshake protocols to access HW functions, which requires a deep understanding of both the HW interfaces and the TLM fabric used. In this paper, we propose our concept of hardware procedure calls (HPC) with which HW services are provided to SW processes as remote methods on top of transaction-level communication. To this end, a lightweight HPC protocol is presented, and we propose a method to generate the infrastructure for HPC communication from a straightforward input description. Our experiments show that with HPC, embedded SW development is considerably made easier, and that also the effort to create the transaction-level model itself is reduced. Copyright 2007 ACM.

关键词： Middleware

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Probabilistic performance risk analysis at system-level

Probabilistic performance risk analysis at system-level

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Viehl, Alexander Schwarz, Markus Bringmann, Oliver Rosenstiel, Wolfgang FZI Forschungszentrum Informatik Haid-und-Neu-Str. 10-14 76131 Karlsruhe Germany Universitat Tubingen Sand 13 72076 Tubingen Germany

ISBN: (纸本)9781595938244

We present a novel hybrid approach for performance analysis of a system design. Unlike other approaches in this area, in this paper we do not focus on the determination of pessimistic best-case and worst-case quantities of system properties. Our proposed analysis methodology determines qualitative numbers between best-case and worst-case of system properties and quantifies them with probabilities. For this issue, we combine local coarse-grained profiling and formal system-level analysis models in a hybrid approach for an early quantitative determination of qualitative system properties. Our approach considers the control-flow of communicating processes and the impact of blocking communication instances on the temporal behavior of the entire system during formal analysis. This can be used for determining the global system performance. The application of our new methodology leads to an inclusion of probabilities concerning system properties and allows an early performance risk estimation of a design with regard to predefined system requirements and constraints. Copyright 2007 ACM.

关键词： Risk analysis

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A data protection unit for NoC-based architectures

A data protection unit for NoC-based architectures

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Fiorin, Leandro Palermo, Gianluca Lukovic, Slobodan Silvano, Cristina ALaRI Faculty of Informatics University of Lugano Via Buffi 13 6904 Lugano Switzerland Politecnico di Milano Dipartimento di Elettronica e Informazione Via Ponzio 34/5 20133 Milano Italy

ISBN: (纸本)9781595938244

Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights (none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit. Copyright 2007 ACM.

关键词： software architecture

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A code-generator generator for multi-output instructions

A code-generator generator for multi-output instructions

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Scharwaechter, Hanno Leupers, Rainer Ascheid, Gerd Meyr, Heinrich Youn, Jonghee M. Paek, Yunheung Integrated Signal Processing Systems RWTH Aachen University Germany Software Optimization and Restructuring Research Group Seoul National University Korea Republic of

ISBN: (纸本)9781595938244

We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very common in the area of Application Specific Instruction Set Processors (ASIPs) and Digital Signal Processors (DSPs) which are frequently used in system-on-Chips as programmable cores. In order to provide high-level programmability, and consequently guarantee widespread acceptance, sophisticated compiler support for these programmable cores is of high importance. Since it is not possible to model Multi-Output Instructions as trees in the compiler's Intermediate Representation (IR), traditional approaches for code selection are not sufficient. Extending traditional code-generation approaches for MOI-selection is essentially a graph covering problem, which is known to be NP-complete. We present a new heuristic algorithm incorporated in a retargetable code-generator generator capable of exploiting arbitrary inherently parallel MOIs. We prove the concept by integrating the tool into the LCC compiler which has been targeted towards different Instruction Set Architectures based on the MIPS architecture. Several network applications as well as some DSP benchmarks were compiled and evaluated to obtain results. Copyright 2007 ACM.

关键词： Automatic programming

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Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems

Dynamic security domain scaling on symmetric multiprocessors...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Inoue, Hiroaki Ikeno, Akihisa Abe, Tsuyoshi Sakai, Junji Edahiro, Masato System IP Core Research Laboratories NEC Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan NEC Informatec Systems Ltd. 3-2-1 Sakado Takatsu-ku Kawasaki Kanagawa 213-0012 Japan

ISBN: (纸本)9781595938244

We propose a method for dynamic security domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources, accomplished by dynamically changing the number of processors within a security domain in response to application load requirements. Two new technologies make this scaling possible without any virtualization software: 1) self-transition management and 2) unified virtual address mapping. Evaluations show that this domain control provides highly scalable performance and incurs almost no performance overhead in security domains. The increase in binary code size is less than 40KB, and the time required for individual state transitions is of a single-millisecond order. This scaling is the first in the world to make possible dynamic changing of the number of processors within a security domain on an ARM SMP. Copyright 2007 ACM.

关键词： Security of data

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software/hardware Engineering with the Parallel Object-Oriented Specification Language 07

Software/Hardware Engineering with the Parallel Object-Orien...

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ACM/IEEE international conference on Formal Methods and Models for Co-Design

作者： Theelen, B. D. Florescu, O. Geilen, M. C. W. Huang, J. van der Putten, P. H. A. Voeten, J. P. M. Eindhoven Univ Technol Dept Elect Engn POB 513 NL-5600 MB Eindhoven Netherlands Eindhoven Univ Technol Embedded Syst Inst NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9781424410507

The complexity of designing hardwarelsoftware systems motivates research on frameworks that structure and automate the design process. Such design methodologies reduce the risk of expensive design-implementation iterations by assisting designers in constructing models. Soflwarelhardware Engineering (SHE) is a general-purpose system-level design methodology that supports analysing bothfunctional correctness and performance properties. SHE combines the Unified Modelling Language with the Parallel Object-Oriented Specification Language to specify models. The designer is assisted in constructing models using these languages and applying the analysis techniques with various guidelines andmodelling patterns. A key feature of SHE is its foundation on formal methods, which ensures that the obtained analysis results are unambiguous. SHE also includes guidelines and techniques for automatic synthesis of real-time control software. This is again based on formal methods to ensure that properties in a model (including real-time properties) are preserved by the software realisation. Finally, to enable an effective and efficient application of the modelling languages as well as the analysis and synthesis techniques, SHE is accompanied with a set of user-friendly tools. This paper gives an overview of SHE, thereby briefly touching upon the underlying mathematical foundation of the analysis and synthesis techniques as well as upon some open issues that require further research.

关键词： hardware Specification languages Object oriented modeling Guidelines software design software systems Process design Design methodology software performance Design engineering

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Three-dimensional multiprocessor system-on-chip thermal optimization

Three-dimensional multiprocessor system-on-chip thermal opti...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Sun, Chong Shang, Li Dick, Robert P. ECE Department Queen's University Kingston ON K7L 3N6 Canada EECS Department Northwestern University Evanston IL 60208 United States

ISBN: (纸本)9781595938244

3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density of 3D MPSoCs increases with the number of active layers, resulting in high chip temperatures. This can reduce system reliability, reduce performance, and increase cooling cost. Thermal optimization for 3D MPSoCs imposes numerous challenges. It is difficult to manage assignment and scheduling of heterogeneous workloads to maintain thermal safety. In addition, the thermal characteristics of 3D MPSoCs differ from those of 2D MPSoCs because each stacked layer has a different thermal resistance to the ambient and vertically-adjacent processors have strong temperature correlation. We propose a 3D MPSoC thermal optimization algorithm that conducts task assignment, scheduling, and voltage scaling. A power balancing algorithm is initially used to distribute tasks among cores and active layers. Detailed thermal analysis is used to guide a hotspot mitigation algorithm that incrementally reduces the peak MPSoC temperature by appropriately adjusting task execution times and voltage levels. The proposed algorithm considers leakage power consumption and adapts to inter-layer thermal heterogeneity. Performance evaluation on a set of multiprogrammed and multithreaded benchmarks indicates that the proposed techniques can optimize 3DMPSoC power consumption, power profile, and chip peak temperature. Copyright 2007 ACM.

关键词： Multiprocessing systems

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Introducing energy and area estimation in HW/SW design flow based on transaction level modeling

Introducing energy and area estimation in HW/SW design flow ...

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18th international conference on Microelectronics (ICM 2006)

作者： Cheema, Muhammad Omer Hammami, Omar ENSTA 32 Blvd Victor F-75739 Paris France

ISBN: (纸本)9781424407644

Transaction Level Modeling (TLM) facilitates the system designer in decision making at early phases of electronic product development. Executable specifications obtained from TLM models are used for the exploration of various architectural parameters and configurations possible for a system. However, traditional design flows based on TLM don't take into account the area and energy consumption of the system which are inevitably the most important constraints in modern embedded system designs. Traditionally, area and energy estimation is incorporated in system design at RTL (Register Transfer Level) which comes later in system design cycles and most of the crucial design decisions for the system has already been taken at that stage. In this paper, we propose a methodology to incorporate area and energy estimation in TLM based system modeling. This methodology allows a system designer take system level design decisions in very early stages of system design hence avoiding redesign efforts and performance bottlenecks in advanced stages of a project. Results obtained by applying our methodology on an image processing application show the robustness of our approach.

关键词： hardware/software codesign behavioral synthesis transaction level modeling area and energy estimation

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Bridging gap between simulation and spreadsheet study

Bridging gap between simulation and spreadsheet study

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Antoine Perrin Frank Ghenassia STMicroelectronics Grenoble France

system architects working on SoC design have traditionally been hampered by the lack of a cohesive methodology for architecture evaluation and co-verification of hardware and software. This paper focuses on a comprehensive analysis framework providing platform assembly facilities, system analysis tools, enhanced traffic model and systemC TLM IP. This framework has been intensively used to design and analyze complex SOC Interconnect based on STBus protocol such as the one of 71xx families. By hiding the complexity of a simulation and filling the gap towards spreadsheet study and costly On-Chip analysis using traffic model, architects benefit from an easy access to an efficient simulation for performance evaluation.

关键词： system-on-a-chip Analytical models Computer architecture Generators Real time systems Bridges Filling

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