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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

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Embedded software development on top of transaction-level models

Embedded software development on top of transaction-level mo...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Wolfgang Klingauf Robert Günzel Christian Schröder Dept. E.I.S. Technical University of Braunschweig Braunschweig Germany

Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write operations via a TLM interconnect. SW developers have to implement platform-specific communication procedures and handshake protocols to access HW functions, which requires a deep understanding of both the HW interfaces and the TLM fabric used. In this paper, we propose our concept of hardware procedure calls (HPC) with which HW services are provided to SW processes as remote methods on top of transaction-level communication. To this end, a lightweight HPC protocol is presented, and we propose a method to generate the infrastructure for HPC communication from a straightforward input description. Our experiments show that with HPC, embedded SW development is considerably made easier, and that also the effort to create the transaction-level model itself is reduced.

关键词： IP networks Fabrics Protocols system-on-a-chip Time domain analysis Time varying systems Object oriented modeling

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A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs

A framework for rapid system-level exploration, synthesis, a...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Mark Thompson Hristo Nikolov Todor Stefanov Andy D. Pimentel Cagkan Erbas Simon Polstra Ed F. Deprettere Department of Computer Science University of Amsterdam Netherlands Leiden Embedded Research Center Leiden University Netherlands

In this paper, we present the Daedalus framework, which allows for traversing the path from sequential application specification to a working MP-SoC prototype in FPGA technology with the (parallelized) application mapped onto it in only a matter of hours. During this traversal, which offers a high degree of automation, guidance is provided by Daedalus' integrated system-level design space exploration environment. We show that Daedalus offers remarkable potentials for quickly experimenting with different MP-SoC architectures and exploring system-level design options during the very early stages of design. Using a case study with a Motion-JPEG encoder application, we illustrate Daedalus' design steps and demonstrate its efficiency.

关键词： Computer architecture Computational modeling Program processors IP networks Field programmable gate arrays XML Space exploration

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ESL design and HW/SW co-verification of high-end software Defined Radio platforms

ESL design and HW/SW co-verification of high-end Software De...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： A. C. H. Ng J. W. Weijers M. Glassee T. Schuster B. Bougard L. Van der Perre IMEC Belgium

Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require handheld platforms to shift from sets of multiple application specific ICs (ASICs) to multi-purpose Multi-Processor system-on-Chip (MPSoC) on which software Defined Radios (SDR) are run. SDR design faces hard real-time processing and data transfer latency constraints. Designing SDR under stringent time-to-market (cost), energy and real-time processing constraints requires the help of advanced Electronic system-Level (ESL) design methodologies. This paper demonstrates an integrated ESL design flow built on advanced ESL tools to design SDR platforms for handhelds. We share the experience from creation of a high-level virtual platform model down to hardware/software (HW/SW) co-verification of a large scale SoC (5 million gates+). Incremental RTL verification based on co-simulation and co-emulation is also presented.

关键词： hardware design languages Emulation Throughput Time domain analysis Time varying systems Synchronization Gain control

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Complex task activation schemes in system level performance analysis

Complex task activation schemes in system level performance ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Wolfgang Haid Lothar Thiele Computer Engineering and Networks Laboratory Swiss Federal Institute of Technology Zurich Switzerland

The design and analysis of today's complex real-time systems requires advanced methods. Due to ever growing functionality, hardware complexity and component interaction, applying traditional methods like HW/SW co-simulation is getting increasingly difficult. On the other hand, analytic approaches have proven their usefulness and efficiency for system analysis when end-to-end performance figures like delay, throughput and memory consumption are requested. One of the main drawbacks of these methods is the limited set of systems that can be analyzed with high accuracy: Only simple models for task interaction and task semantics can be used. In this paper, we extend existing methods for analyzing heterogeneous multiprocessor systems such that (a) non-preemptive scheduling policies, (b) complex activation schemes for tasks and (c) conditional behavior of task executions can be modeled and analyzed. We demonstrate the usefulness of the proposed approach in a case study.

关键词： Analytical models Delay Decoding Performance analysis Processor scheduling Embedded systems Algorithm design and analysis

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Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC

Simultaneous synthesis of buses, data mapping and memory all...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Brett H. Meyer Donald E. Thomas Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the target applications, these systems will also have custom memory and bus architectures. Because of performance and cost constraints, these systems must be carefully designed to balance system partitioning and resource sharing. The sheer size of the design space requires that tools be able to do this balancing. We have developed an augmented simulated annealing synthesis tool that uses system performance and layout evaluation to drive simultaneous data mapping, memory allocation and bus synthesis. Performing these optimizations at the same time, our tool is able to explore a larger design space and take advantage of cost-saving resource sharing unavailable to previous approaches that allocate memories before synthesizing buses. This results in 20% cost reduction for high-performance designs as well as 27% for low-cost designs in comparison with an approach that performs memory allocation and data mapping separately from bus synthesis.

关键词： Resource management Annealing Topology Wire Libraries Limiting Space exploration

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Thread warping: A framework for dynamic synthesis of thread accelerators

Thread warping: A framework for dynamic synthesis of thread ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Greg Stitt Frank Vahid Department of Electrical and Computer Engineering University of Florida USA Department of Computer Science and Engineering University of California Riverside USA Center of Embedded Computer Systems University of California Irvine USA

We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding up individual threads and by allowing more threads to execute concurrently. Furthermore, thread warping maintains the important separation of function from architecture, enabling portability of applications to architectures with different quantities of microprocessors and FPGA-an advantage not shared by static compilation/synthesis approaches. We introduce a framework of architecture, CAD tools, and operating system that together support thread warping. We summarize experiments on an extensive architectural simulation framework we developed, showing application speedups of 4× to 502×, averaging 130× compared to a multiprocessor system having four ARM11 microprocessors, for eight benchmark applications. Even compared to a 64-processor system, thread warping achieves 11× speedup.

关键词： Instruction sets Field programmable gate arrays Design automation Synchronization Microprocessors system-on-a-chip

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A data protection unit for NoC-based architectures

A data protection unit for NoC-based architectures

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Leandro Fiorin Gianluca Palermo Slobodan Lukovic Cristina Silvano ALaRI-Faculty of Informatics University of Lugano Lugano Switzerland Dipartimento di Elettronica e Informazione Politecnico di Milano Milan Italy

Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights (none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit.

关键词： Computer architecture Nickel Random access memory Permission Computer aided manufacturing system-on-a-chip

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Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems

Dynamic security domain scaling on symmetric multiprocessors...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hiroaki Inoue Akihisa Ikeno Tsuyoshi Abe Junji Sakai Masato Edahiro Nihon Denki Kabushiki Kaisha Minato-ku Tokyo JP NEC Informatec Systems Ltd. Kawasaki Kanagawa Japan NEC Corporation System IP Core Research Laboratories Sagamihara Kanagawa Japan

We propose a method for dynamic security domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources, accomplished by dynamically changing the number of processors within a security domain in response to application load requirements. Two new technologies make this scaling possible without any virtualization software: 1) self-transition management and 2) unified virtual address mapping. Evaluations show that this domain control provides highly scalable performance and incurs almost no performance overhead in security domains. The increase in binary code size is less than 40 KB, and the time required for individual state transitions is of a single-millisecond order. This scaling is the first in the world to make possible dynamic changing of the number of processors within a security domain on an ARM SMP.

关键词： Security Context Registers Embedded systems Switches Process control

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Ensuring secure program execution in multiprocessor embedded systems: A case study

Ensuring secure program execution in multiprocessor embedded...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Krutartha Patel Sri Parameswaran Seng Lin Shee School of Computer Science and Engineering University of New South Wales Sydney Australia

Multiprocessor SoCs are increasingly deployed in embedded systems with little or no security features built in. Code Injection attacks are one of the most commonly encountered security threats. Most solutions to this problem in the single processor domain are purely software based and have high overheads. A few hardware solutions have been provided for the single processor case, which significantly reduce overheads. In this paper, for the first time, we propose a methodology addressing code injection attacks in a multiprocessor domain. A dedicated security (monitor) processor is used to oversee the application at runtime. Each processor communicates with the monitor processor through a FIFO queue, and is continuously checked. Static analysis of program map and timing profile are used to obtain program information at compile time, which is utilized by the monitor processor at runtime. This information is encrypted using a secure key and stored in the monitor processor. A copy of this secure key is built into the processor's hardware and is used for decryption by the monitor processor. Each basic block of the program is also instrumented with security information that uniquely identifies itself at runtime. The information from static analysis thus allows the monitor processor to supervise the proceedings on each processor at runtime. Our approach uses a combination of hardware and software techniques to keep overheads to a minimum. We implemented our methodology on a commercial extensible processor (Xtensa LX). Our approach successfully detects the execution of injected code when tested on a JPEG multiprocessor benchmark. The results show a small increase of 6.6% in application processors' runtime (clock cycle count) and 35.2% in code size for the JPEG encoder benchmark.

关键词： Security Runtime Monitoring hardware Benchmark testing Transform coding software

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A code-generator generator for Multi-Output Instructions

A code-generator generator for Multi-Output Instructions

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hanno Scharwaechter Rainer Leupers Gerd Ascheid Heinrich Meyr Jonghee M. Youn Yunheung Paek Integrated Signal Processing Systems RWTH Aachen University Germany Software Optimization & Restructuring Research Group Seoul National University South Korea

We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very common in the area of Application Specific Instruction Set Processors (ASIPs) and Digital Signal Processors (DSPs) which are frequently used in system-on-Chips as programmable cores. In order to provide high-level programmability, and consequently guarantee widespread acceptance, sophisticated compiler support for these programmable cores is of high importance. Since it is not possible to model MultiOutput Instructions as trees in the compiler's Intermediate Representation (IR), traditional approaches for code selection are not sufficient. Extending traditional code-generation approaches for MOI-selection is essentially a graph covering problem, which is known to be NP-complete. We present a new heuristic algorithm incorporated in a retargetable code-generator generator capable of exploiting arbitrary inherently parallel MOIs. We prove the concept by integrating the tool into the LCC compiler which has been targeted towards different Instruction Set Architectures based on the MIPS architecture. Several network applications as well as some DSP benchmarks were compiled and evaluated to obtain results.

关键词： Grammar Program processors Generators Assembly Pattern matching Protocols Encryption

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