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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Woo, Nam-Sung Samsung Electronics

ISBN: (纸本)1595933700

Recent trends of IT industry include Mobile/Portable Solution, Integration and Faster Time-to-Market. These trends impose many interesting challenges to Embedded system development both in hardware and software. In this talk, we will first identify some of the challenges. Then, we will present both the current status and plans of Samsung Electronics (in particular, Samsung Semiconductor) to address and overcome the challenges. © Copyright 2006 ACM.

关键词： Information technology

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hardware /software codesign of image processing applications using transaction level modeling

Hardware /software codesign of image processing applications...

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CAMPS 2006 - international Workshop on Computer Architecture for Machine Perception and Sensing

作者： Cheema, Muhammad Orner Hammami, Omar Lacassagne, Lionel Merigot, Alain ENSTA 32 Boulevard Victor 75739 Paris France IEF University of Paris Sud 91405 Orsay France

ISBN: (纸本)1424406862

Transaction Level Modeling (TLM) and component based software development approaches accelerate the process of an embedded system design and simulation and hence improve the overall productivity. On the other hand, system level design languages facilitate the fast hardware synthesis at behavioral level of abstraction. In this paper, we introduce an approach for hardware/software codesign of image processing application that uses TLM and component based software design approaches along with HW synthesis using systemC to accelerate system design and verification process. Our experiments performed over an image processing application shows the effectiveness of our methodology. © 2006 IEEE.

关键词： hardware-software codesign

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A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH

A unified hardware/software runtime environment for FPGA-bas...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： So, Hayden Kwok-Hay Tkachenko, Artem Brodersen, Robert Department of Electrical Engineering and Computer Science University of California Berkeley

ISBN: (纸本)1595933700

This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel support for FPGA hardware, BORPH offers a homogeneous UNIX interface for both software and hardware processes. hardware processes inherit the same level of service from the kernel, such as file system support, as typical UNIX software processes. hardware and software components of a design therefore run as hardware and software processes within BORPH's run-time environment. The familiar and language independent UNIX kernel interface facilitates easy design reuse and rapid application development. Performance of our current implementation and our experience with developing a real-time wireless digital signal processing system based on BORPH will be presented. © Copyright 2006 ACM.

关键词： Field programmable gate arrays (FPGA)

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system-level power-performance tradeoffs for reconfigurable computing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 730-739页

作者： Noguera, Juanjo Badia, Rosa M. Tech Univ Catalonia Comp Architecture Dept Barcelona 08034 Spain

In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing, We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applications, we show that an efficient hardware/software partitioning algorithm is required when targeting low power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. We propose a design methodology that adapts the architecture and algorithms to the application requirements. The methodology hag been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology, and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.

关键词： hardware/software (HW/SW) codesign power-performance tradeoffs reconfigurable computing (RC)

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hardware estimation and synthesis for a codesign system

Hardware estimation and synthesis for a codesign system

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international conference on Signal Processing, Communications and Networks

作者： Sangeetha, M. Perinbam, J. RajaPaul Revathy Anna Univ Coll Engn Dept Elect & Commun Engn Madras 600025 Tamil Nadu India SA Engn Coll Dept Elect & Commun Engn Madras Tamil Nadu India

ISBN: (纸本)9781424409969

A software model of hardware estimator is developed. The behavioral description is transformed into an intermediate format called Control Flow Graph (CFG). The graph is partitioned into hardware and software. The unoptimized hardware in intermediate graph is estimated by transforming the graph into matrix format. The partitioned hardware of Control Flow Graph is translated as behavioral network graph. The High Level synthesis and Logic synthesis are performed using the BNG with simple logical transformation. The final RTL obtained from the conventional synthesis method and BNG method for resource and timing constraint were presented. The cost estimation for the various control construction is being tabulated.

关键词： Codes (symbols)

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Increasing hardware efficiency with multifunction loop accelerators

Increasing hardware efficiency with multifunction loop accel...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Fan, Kevin Kudlur, Manjunath Park, Hyunchul Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595933700

To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally designed in a single-function manner, wherein each loop nest is implemented as a dedicated hardware block. This paper focuses on hardware sharing across loop nests by creating multifunction loop accelerators, or accelerators capable of executing multiple algorithms. A compiler-based system for automatically synthesizing multifunction loop accelerator architectures from C code is presented. We compare the effectiveness of three architecture synthesis approaches with varying levels of complexity: sum of individual accelerators, union of individual accelerators, and joint accelerator synthesis. Experiments show that multifunction accelerators achieve substantial hardware savings over combinations of single-function designs. In addition, the union approach to multifunction synthesis is shown to be effective at creating low-cost hardware by exploiting hardware sharing, while remaining computationally tractable. © Copyright 2006 ACM.

关键词： Computer hardware

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Streamroller: Automatic synthesis of prescribed throughput accelerator pipelines

Streamroller: Automatic synthesis of prescribed throughput a...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Kudlur, Manjunath Fan, Kevin Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595933700

In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylizations. The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating buffers for arrays used in the application, and hooking up these building blocks to form a pipeline. A compiler-based system automatically synthesizes loop accelerators for individual kernels at varying performance levels. An integer linear program formulation which simultaneously optimizes the cost of loop accelerators and the cost of memory buffers is proposed to compose the loop accelerators to form an accelerator pipeline for the whole application. Cases studies for some applications, including FMRadio and Beamformer, are presented to illustrate our design methodology. Experiments show significant cost savings are achieved through hardware sharing, while achieving the prescribed throughput requirements. © Copyright 2006 ACM.

关键词： Pipeline processing systems

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hardware based frequency/voltage control of voltage frequency island systems

Hardware based frequency/voltage control of voltage frequenc...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Choudhary, Puru Marculescu, Diana Dept. of Electrical and Computer Engineering Carnegie Mellon University 5000 Forbes Ave. Pittsburgh PA 15213

ISBN: (纸本)1595933700

The ability to do fine grain power management via local voltage selection has shown much promise via the use of Voltage/Frequency Islands (VFIs). VFI-based designs combine the advantages of using fine-grain speed and voltage control for reducing energy requirements, while allowing for maintaining performance constraints. We propose a hardware based technique to dynamically change the clock frequencies and potentially voltages of a VFI system driven by the dynamic workload. This technique tries to change the frequency of a synchronous island such that it will have efficient power utilization while satisfying performance constraints. We propose a hardware design that can be used to change the frequencies of various synchronous islands interconnected together by mixed-clock/mixed-voltage FIFO interfaces. Results show up to 65% power savings for the set of benchmarks considered with no loss in throughput. © Copyright 2006 ACM.

关键词： Voltage control

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Automotive electronics system, software, and local area network 06

Automotive electronics system, software, and local area netw...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Furukawa, Yoshimi Kawamura, Seiji Shibaura Institute of Technology Saitama Japan AutoNetworks Technologies Ltd. Yokkaichi Japan

ISBN: (纸本)1595933700

In this tutorial, an overview of automotive electronic systems and details of the development methodologies are presented. Automobiles were born to enhance human mobile performance. In early development stage, automotive engineers focused to strengthen automobile engine power. Afterwards, automobiles had enough function to drive faster than any animal, but they caused some social problems such as traffic accidents, environmental problems and traffic congestions. Automotive electronic technologies have been developed in order to solve these social *** of electronic technologies on automobile functional developments For the solution to safety, environment and traffic problems, various functions are necessary which could not be completed only by mechanical systems. In this section, roles of automobile electronic systems on countermeasures to the social problems are discussed. Vehicle motion control systems, power-train control systems, navigation systems, and advanced drive assist systems are introduced and automotive functions are defined. Design requirement for automotive electronic systems architecture Electronic systems composed basically of sensors, ECU's (Electronic Control Units), actuators and human interfaces. In early days, each electronic system was designed independently. Today's automobile has various functions which could be completed by multiple electric systems. Therefore, fundamental architecture of integrated electronic systems in an automobile is important to be designed in order to optimize the total function, cost and *** and development procedure of electronic systems and software In vehicle systems and software, required functions and complexity of products are increasing. In this situation, ECU suppliers are working with efficient development methodology to achieve the highest quality. Today most common development processes are still classical V shaped process, module design and C language programming. However, severa

关键词： Automotive engineering

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Platform-based behavior-level and system-level synthesis

Platform-based behavior-level and system-level synthesis

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IEEE international SOC conference

作者： Cong, Jason Fan, Yiping Han, Guoling Jiang, Wei Zhang, Zhiru Univ Calif Los Angeles Los Angeles CA 90001 USA

ISBN: (纸本)0780397819

With the rapid increase of complexity in system-on-a-Chip (SoC) design, the electronic design automation (EDA) community is moving from RTL (Register 'IYansfer Level) synthesis to behavioral-level and system-level synthesis. The needs of system-level verification and software/hardware codesign also prefer behavior-level executable specifications, such as C or systemC. In this paper we present the platform-based synthesis system, named xPilot, being developed at UCLA. The first objective of xPilot is to provide novel behavioral synthesis capability for automatically generating efficient RTL code from a C or systemC description for a given system platform and optimizing the logic, interconnects, performance, and power simultaneously. The second objective of xPilot is to provide a platform-based system-level synthesis capability, including both synthesis for application-specific configurable processors and heterogeneous multi-core systems. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs.

关键词： Microprocessor chips

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