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Challenges in exploitation of loop parallelism in embedded applications

Challenges in exploitation of loop parallelism in embedded a...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hideki Saito Alexander V. Veidenbaum Xinmin Tian Milind Girkarmark Alexandru Nicolau Arun Kejariwal Center for Embedded Computer Systems University of California at Irvine Irvine CA USA Intel Corporation Santa Clara CA USA

Embedded processors have been increasingly exploiting hardware parallelism. Vector units, multiple processors or cores, hyper-threading, special-purpose accelerators such as DSPs or cryptographic engines, or a combination of the above have appeared in a number of processors. They serve to address the increasing performance requirements of modern embedded applications. How this hardware parallelism can be exploited by applications is directly related to the amount of parallelism inherent in a target application. In this paper we evaluate the performance potential of different types of parallelism, viz., true thread-level parallelism, speculative thread- level parallelism and vector parallelism, when executing loops. Applications from the industry-standard EEMBC 1.1, EEMBC 2.0 and the MiBench embedded benchmark suites are analyzed using the Intel C compiler. The results show what can be achieved today, provide upper bounds on the performance potential of different types of thread parallelism, and point out a number of issues that need to be addressed to improve performance. The latter include parallelization of libraries such as libc and design of parallel algorithms to allow maximal exploitation of parallelism. The results also point to the need for developing new benchmark suites more suitable to parallel compilation and execution.

关键词： Parallel processing hardware Parallel programming Cryptography Multithreading Engines software libraries software engineering software measurement Permission

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A formal approach to robustness maximization of complex heterogeneous embedded systems

A formal approach to robustness maximization of complex hete...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Razvan Racu Rolf Ernst Arne Hamann Institute of Computer and Communication Network Engineering Technical University of Braunschweig Germany

Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variations of properties like execution and transmission delays, input data rates, CPU clock rates, etc., has found less attention despite its practical relevance. In this paper we introduce robustness metrics and propose an algorithm considering these metrics in design space exploration and system optimization. The algorithm can optimize for static and for dynamic robustness, the latter including system or designer reactions to property variations. We explain several applications ranging from platform optimization to critical component identification. By means of extensive experiments we show that design space exploration pursuing classical design goals does not necessarily yield robust systems, and that our method leads to systems with significantly higher design robustness.

关键词： Robustness Embedded system Algorithm design and analysis Space exploration Design optimization Cost function Timing Energy consumption Delay Clocks

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Layout aware design of mesh based NoC architectures

Layout aware design of mesh based NoC architectures

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Karam S. Chatha Krishnan Srinivasan Department of Computer Science and Engineering Arizona State University Tempe AZ USA

Design of system-on-chip (SoC) with regular mesh based network-on-chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology such that power consumption is minimized, and performance constraints are satisfied. Technology scaling increases the contribution of the link power to the overall power consumption of the NoC. Since link power consumption is dependent on the length of the link, its contribution cannot be accurately estimated without system-level floorplanning. In this paper, we propose a novel design technique that integrates system- level floorplanning into the NoC design flow. Our technique invokes an existing floorplanner to generate an initial layout of the cores. This is followed by invocation of a novel low complexity algorithm that generates the mesh based NoC architecture with complete information of the floorplan. In comparison to an existing approach, our technique results in lower total power consumption and much lower link power consumption.

关键词： Network-on-a-chip Energy consumption Computer architecture Mesh generation Routing Bandwidth Topology Computer science Design engineering system-on-a-chip

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system-level power-performance trade-offs in bus matrix communication architecture synthesis

System-level power-performance trade-offs in bus matrix comm...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Young-Hwan Park Fadi J. Kurdahi Nikil Dutt Sudeep Pasricha Center for Embedded Computer Systems University of California Irvine CA USA

system-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, power- performance trade-offs in bus matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of bus matrix communication architectures. Second, we incorporate these macro- models into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our energy macro- models incur less than 5% average absolute error compared to gate-level models. Furthermore, our bus matrix synthesis framework generates a tradeoff space with designs that exhibits an approximately 20% variation in power and 40% variation in performance on an industrial networking MPSoC application, demonstrating the utility of our approach.

关键词： Energy consumption Computer architecture system-on-a-chip Space exploration Bandwidth Integrated circuit synthesis Network-on-a-chip Embedded computing Multiprocessing systems Application software

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Automatic generation of transaction level models for rapid design space exploration

Automatic generation of transaction level models for rapid d...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Junyu Peng Andreas Gerstlauer Daniel D. Gajski Rainer Domer Dongwan Shin Center for Embedded Computer Systems University of California Irvine CA USA

Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate such transaction-level models from abstract input descriptions. Designers have to write such models manually, which is a tedious and error-prone task, and one of bottlenecks in improving designer's productivity. In this paper, we propose a method to generate transaction-level models from virtual architecture models where components communicate via abstract message-passing channels. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness and benefits of our approach for rapid, early exploration of communication design space.

关键词： Space exploration Computational modeling Productivity system-on-a-chip Permission Concrete Embedded computing Computer simulation Design automation system-level design

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Accurate yet fast modeling of real-time communication

Accurate yet fast modeling of real-time communication

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Rainer Domer Gunar Schirner Center for Embedded Computer Systems University of California Irvine USA

Accurate modeling of communication is a necessary part of system level design for real-time safety-critical applications. For efficient prediction of a system's performance, transaction level modeling (TLM) is often used which increases the simulation speed by orders of magnitude. The speed advantage, however, comes at the cost of low accuracy. In this paper, we use a novel modeling technique, called result oriented modeling (ROM), which yields 100% accuracy in timing, yet approaches the same speed as traditional TLM. ROM also abstracts away internal details of the communication but, in contrast to TLM, fully maintains accurate timing. ROM optimistically predicts the timing and retroactively takes corrective measures, if necessary. In this paper, we compare the ROM technique to TLM at different levels of abstraction, using a controller area network (CAN) bus example. Our results show that ROM yields a simulation speedup close to the traditional TLM, yet exhibits the same timing accuracy as a bus functional model. Thus, for safety-critical real-time applications, ROM is a viable replacement for the inaccurate TLM.

关键词： Read only memory Timing Predictive models Accuracy system-level design Real time systems system performance Costs Abstracts Communication system control

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Generic netlist representation for system and PE level design exploration

Generic netlist representation for system and PE level desig...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Pramod Chandraiah Mehrdad Reshadi Daniel Gajski Bita Gorjiara Center for Embedded Computer Systems University of California Irvine USA

Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems require more productive design approaches starting from high-level languages such as C. On the other hand, tight constraints of embedded systems require careful design exploration at system level (coarse grained exploration) and at the processing-element (PE) level (fine grained exploration). In this paper we presented GNR, a formal modeling approach, developed to improve productivity of designing systems and processing elements, the same way that traditional ADLs improved productivity for designing processors. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. Using relatively short GNR description, we explored several designs for implementing an MP3 decoder and achieved 3.25 speedup compared to MicroBlaze processor. We have also developed a Web-based interface for our tools, so that users can upload and evaluate new architectures described in GNR Our toolset and GNR is an intermediate step towards synthesis of TLM to RTL.

关键词： Productivity Embedded system Process design Decoding Application specific processors hardware Automatic control Embedded computing Time to market High level languages

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Application-specific workload shaping in multimedia-enabled personal mobile devices

Application-specific workload shaping in multimedia-enabled ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Samarjit Chakraborty Balaji Raman Department of Computer Science National University of Singapore Singapore

Today, most personal mobile devices (e.g. cell phones and PDAs) are multimedia-enabled and support a variety of concurrently running applications such as audio/video players, word processors and Web browsers. Media-processing applications are often computationally expensive and most of these devices typically have 100 - 400 MHz processors. As a result, the user-perceived application response times are often poor when multiple applications are concurrently fired. In this paper we show that by using application-specific dynamic buffering techniques, the workload of these applications can be suitably "shaped" to fit the available processor bandwidth. Our techniques are analogous to traffic shaping which is widely used in communication networks to optimally utilize network bandwidth. Such shaping techniques have recently attracted a lot of attention in the context of embedded systems design (e.g. for dynamic voltage scaling). However, they have not been exploited for enhanced schedulability of multiple applications, as we do in this paper.

关键词： Bandwidth Cellular phones Personal digital assistants Computer applications Delay Telecommunication traffic Communication networks Context Embedded system Dynamic voltage scaling

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Are current ESL tools meeting the requirements of advanced embedded systems?

Are current ESL tools meeting the requirements of advanced e...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jurgen Teich University of Erlangen Nuremberg Germany

Electronic system Level (ESL) tools are becoming more and more important in order to bridge the well-known productivity design gap. This panel brings together specialists from industry and ESL tool houses to discuss whether current ESL tools available are usable and meeting the requirements of the industry. In particular, we would like to know to what degree currently available tools from major ESL tool houses are used for designing what kind of systems in industry, and for what purpose such as analysis, design space exploration, or synthesis, etc. these tools are currently used. Also, we would like to discuss to what degree existing tools can help in reducing design time, and finally, what the industry sees the most challenging features of tools currently not yet available. On the other side, we would like to know the opinion of the ESL tool houses what they see the most important offerings of ESL tools currently available as well as the most challenging points and problems why ESL hasn't really taken off so far. Could this either be an industry issue, a methodology issue, a design issue or a tool issue?

关键词： Embedded system Bridges Productivity Aerospace industry Space exploration Design methodology Electronics industry Microelectronics Electronic design automation and methodology Design automation

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Methodology for attack on a Java-based PDA

Methodology for attack on a Java-based PDA

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international conference on hardware/software codesign and system synthesis (CODES)

作者： B. A. White C. H. Gebotys Department of Electrical and Computer Engineering University of Waterloo ONT Canada

Although mobile Java code is frequently executed on many wireless devices, the susceptibility to electromagnetic (EM) attacks is largely unknown. If analysis of EM waves emanating from the wireless device during a cryptographic computation does leak sufficient information, it may be possible for an attacker to reconstruct the secret key. Possession of the secret cryptographic key would render all future wireless communications insecure and cause further potential problems such as identity theft. Despite the complexities of a Java-based PDA device, this paper proposes and verifies a methodology which confirms EM attacks are possible. The proposed methodology involves pre-characterization of the PDA device through SEMA, thresholding, pattern recognition, and frequency-based DEMA. Results are repeatable over several different secret keys. Unlike previous research the new methodology does not require perfect alignment of EM frames and demonstrates robustness in the presence of a complex embedded system. This research is important for future wireless embedded systems which will increasingly demand higher levels of security.

关键词： Java Personal digital assistants Cryptography Embedded system Electromagnetic devices Information analysis Wireless communication Pattern recognition Frequency Robustness

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