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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 852 条记录，以下是51-60 订阅

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Work-in-Progress: A Unified Framework for Throughput Analysis of Synchronous Data Flow Graphs under Memory Constraints 12

Work-in-Progress: A Unified Framework for Throughput Analysi...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Zhu, Xue-Yang Chinese Acad Sci Inst Software State Key Lab Comp Sci Beijing 100190 Peoples R China

ISBN: (纸本)9781450351850

Streaming applications are often modeled with Synchronous data flow graphs (SDFGs). A proper analysis of the models is helpful to predict the performance of a system. In this paper, we focus on the throughput analysis of memory-constrained SDFGs (MC SDFGs), which needs to choose a memory abstraction that decides when the space of consumed data is released and when the required space is claimed. Different memory abstractions may lead to different achievable throughputs. The existing techniques, however, consider only a certain abstraction. If a model is implemented according to other abstractions, the analysis result may not truly evaluate the performance of the system. In this paper, we present a unified framework for throughput analysis of MC SDFGs for difference abstractions, aiming to provide evaluations matching up to the corresponding implementations.

关键词： Throughput Memory management Computational modeling Analytical models Electromagnetic compatibility Data models Flow graphs

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RTOS-centric hardware/software cosimulator for embedded system design

RTOS-centric hardware/software cosimulator for embedded syst...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Honda, S Wakabayashi, T Tomiyama, H Takada, H Toyohashi Univ Technol Dept Informat & Comp Sci Toyohashi Aichi 4418580 Japan

ISBN: (纸本)1581139373

This paper presents an RTOS-centric hardware/software cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is that it has a complete simulation model of an RTOS which is widely used in industry, so that application tasks including RTOS service calls are natively executed on a host computer. Our cosimulator also features cosimulation with functional simulation models of hardware written in C/C++ and cosimulation with HDL simulators. A case study with a JPEG decoder application demonstrates the effectiveness of our cosimulator.

关键词： RTOS cosimulation embedded systems

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hardware support for real-time operating systems

Hardware support for real-time operating systems

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Kohout, P Ganesh, B Jacob, B EVI Technol LLC Columbia MD 21046 USA

ISBN: (纸本)1581137427

The growing complexity of embedded applications and pressure on time-to-market has resulted in the increasing use of embedded real-time operating systems. Unfortunately, RTOSes can introduce a significant performance degradation. This paper presents the Real-Time Task Manager (RTM)-a processor extension that minimizes the performance drawbacks associated with RTOSes. The RTM accomplishes this by supporting, in hardware, a few of the common RTOS operations that are performance bottlenecks: task scheduling, time management, and event management. By exploiting the inherent parallelism of these operations, the RTM completes them in constant time, thereby significantly reducing RTOS overhead. It decreases both the processor time used by the RTOS and the maximum response time by an order of magnitude.

关键词： RTOS hardware software codesign

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A codesigned on-chip logic minimizer

A codesigned on-chip logic minimizer

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Lysecky, R Vahid, F Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)1581137427

Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic use in embedded systems, including network route table reduction, network access control list table reduction, and dynamic hardware/software partitioning. These now uses require logic minimization to run dynamically as part of an embedded system's active operation. Performing such dynamic logic minimization on-chip greatly reduces system complexity and security versus an approach that involves communication with a desktop logic minimizer. An on-chip minimizer must be exceptionally lean yet yield good enough results. Previous software-only on-chip minimizer results have been good, but we show that a codesigned minimizer can be much better, executing nearly 8 times faster and consuming nearly 60% less energy, while yielding identical results.

关键词： logic minimization dynamic optimization on-chip logic minimization on-chip synthesis system-on-a-chip embedded systems hardware/software codesign embedded CAD

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RTOS scheduling in transaction level models 03

RTOS scheduling in transaction level models

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Yu, HB Gerstlauer, A Gajski, D Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA

ISBN: (纸本)1581137427

Raising the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impact on system performance, it's much desired that the designer can select the right scheduling algorithm at high abstraction levels so as to save him from the error-prone and time consuming task of tuning code delays or task priority assignments at the final stage of system design. In this paper we tackle this problem by introducing a RTOS model and an approach to refine any unscheduled transaction level model (TLM) to a TLM with RTOS scheduling support. The refinement process provides a useful tool to the system designer to quickly evaluate different dynamic scheduling algorithms and make the optimal choice at the early stage of system design.

关键词： RTOS SpecC system design model

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Work-in-Progress: Runtime Requirements Monitoring for State-based hardware

Work-in-Progress: Runtime Requirements Monitoring for State-...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Seo, Minjun Lysecky, Roman Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

ISBN: (纸本)9781538655627

This paper presents a requirements-driven methodology enabling efficient runtime monitoring of hardware in embedded systems. We present a novel method for extracting hardware verification requirements from state-based hardware models to construct a hierarchical runtime monitoring graph (HRMG) that can be efficiently used at runtime to verify correctness.

关键词： Runtime requirements verification hardware verification formal verification models non-intrusive monitoring

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Rapid prototyping of reconfigurable coprocessors

Rapid prototyping of reconfigurable coprocessors

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international conference on Application-Specific systems, Architectures and Processors

作者： Narasimhan, N Srinivasan, V Vootukuru, M Walrath, J Govindarajan, S Vemuri, R UNIV CINCINNATI DEPT ECECSLAB DIGITAL DESIGN ENVIRONMCINCINNATIOH 45221

ISBN: (纸本)081867542X

We describe the process of hardware-software codesign of a JPEG-like still image compression system. The hardware components are targeted to execute on a reconfigurable hardware coprocessor which communicates with a host computer that executes all the software tasks. Central to our codesign methodology is the usage of software profiling, high-level estimation and synthesis tools. We describe the process of trade-off analysis and hardware task selection in detail. We present detailed experimental results gathered throughout the codesign process.

关键词： Coprocessors rapid prototyping on line data service task selection hardware/software co-design compression system configurability Computer hardware JPEG Still images reconfigurable hardware

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Work-in-Progress: hardware Implementation of a Multi-Mode-Aware Mixed-Criticality Scheduler

Work-in-Progress: Hardware Implementation of a Multi-Mode-Aw...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hounsinou, Sena Vasu, Aishwarya Ramaprasad, Harini Southern Illinois Univ Carbondale IL 62901 USA Univ N Carolina Charlotte NC USA

ISBN: (纸本)9781538655627

To minimize size, weight, power, and cost, the industry aims at consolidating different criticality applications on the same hardware platform. In such a mixed-criticality environment, it is challenging to contain the overhead due to potential mode changes under overload conditions. Traditional scheduler implementation at the software level introduces additional overheads due to timer interrupt processing and context switching. To minimize overall software overhead and to improve timing predictability, in this paper, we propose an implementation of the mixed-criticality scheduler in the hardware that is capable of detecting task-overruns and making mode transitions seamlessly.

关键词： Task analysis hardware Real-time systems Monitoring Registers software Processor scheduling

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system-level design automation tools for digital microfluidic biochips 05

System-level design automation tools for digital microfluidi...

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international conference on hardware/software codesign and system synthesis

作者： Chakrabarty, K Su, F Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA

ISBN: (纸本)1595931619

Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom design techniques for digital microfluidic biochips do not scale well for increasing levels of system integration. Analogous to classical VLSI synthesis, a top-down system-level design automation approach can shorten the biochip design cycle and reduce human effort. We present here an overview of a system-level design methodology that includes architectural synthesis and physical design. The proposed design automation approach is expected to relieve biochip users from the burden of manual optimization of bioassays.. time-consuming hardware design, and costly testing and maintenance procedures.

关键词： synthesis physical design microfluidics biochip

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hardware-software codesign of multimedia embedded systems: the PeaCE approach

Hardware-software codesign of multimedia embedded systems: t...

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12th international conference on Embedded and Real-Time Computing systems and Applications

作者： Ha, Soonhui Lee, Choonseung Yi, Youngmin Kwon, Seongnam Joo, Young-Pyo Seoul Natl Univ CAP Lab Seoul South Korea

ISBN: (纸本)0769526764

hardware/software codesign involves various design problems including system specification, design space exploration, hardware/software co-verification, and system synthesis. A codesign environment is a software tool that facilitates capabilities to solve these design problems. This paper presents the PeaCE codesign environment mainly targeting for multimedia applications with real-time constraints. PeaCE specifies the system behavior with a heterogeneous composition of three models of computation. The PeaCE environment provides seamless co-design flow from functional simulation to system synthesis, utilizing the features of the formal models maximally during the whole design process. Preliminary experiments with real examples prove the viability of the proposed technique.

关键词： Embedded systems

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