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Fuzzy decision making in embedded system design

Fuzzy decision making in embedded system design

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Vincenzo Catania Giuseppe Ascia Maurizio Palesi Davide Patti Alessandro G. Di Nuovo Universita degli Studi di Catania Catania Sicilia IT DIIT Università di Catania Catania Italy Dipartimento di Ingegneria Informatica e delle Telecomunicazioni Università degli Studi di Catania Catania Italy

The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of increasing complexity in embedded systems design. One of the major challenges in ASIP design is Design Space Exploration (DSE), because of the heterogeneity of the objectives and parameters involved. Typically DSE is a multi- objective search problem, where performance, power, area, etc. are the different optimization criteria. The output of a DSE strategy is a set of candidate design solutions called a Pareto-optimal set. Choosing a solution for system implementation from the Pareto- optimal set can be a difficult task, generally because Pareto-optimal sets can be extremely large or even contain an infinite number of solutions. In this paper we propose a methodology to assist the decision-maker in analysis of the solutions to multi-objective problems. By means of fuzzy clustering techniques, it finds the reduced Pareto subset, which best represents all the Pareto solutions. This optimal subset will be used for further and more accurate (but slower) analysis. As a real application example we address the optimization of area, performance, and power of a VLIW-based embedded system.

关键词： Fuzzy systems Decision making Embedded system Space exploration Application specific processors Computational modeling Computer simulation Computer applications Algorithm design and analysis Design optimization

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Thermal-aware high-level synthesis based on network flow method

Thermal-aware high-level synthesis based on network flow met...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Taewhan Kim Pilok Lim School of Electrical Enginnering and Computer Science Seoul National University Seoul South Korea

Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and leakage power of chip, and also increases the packaging cost. In this work, we address a new problem of thermal-aware module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. The two key contributions are (1) to solve the binding problem with the primary objective of minimizing the 'peak' switched capacitance of modules and the secondary objective of minimizing the 'total' switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the 'peak' heat diffusion between modules. For (1), our proposed thermal-aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a floorplan information, if exists, of modules to be practically effective. From experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1degC and 11.8degC lower peak temperature on the average, compared to that of the conventional low-power and thermal- aware methods, which target to minimizing total switched capacitance only ([18]) and to minimizing peak switched capacitance only ([16]), respectively.

关键词： High level synthesis Capacitance Energy consumption Equations Temperature measurement Iterative algorithms Computer science Computer network reliability Packaging Costs

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Floorplan driven leakage power aware IP-based SoC design space exploration

Floorplan driven leakage power aware IP-based SoC design spa...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Kamal Khouri Fadi Kurdahi Magdy Abadir Nikil Dutt Aseem Gupta Center for Embedded Computer Systems University of California Irvine CA USA Design Technology Organization Freescale Semiconductor Inc. Austin TX USA

Multi-million gate system-on-chip (SoC) designs increasingly rely on intellectual property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP blocks has risen thus leading to possible thermal runaway. In IP-based design there has been a disconnect between system level design and physical level steps such as floorplanning which can lead to failures in manufactured chips. This necessitates coupling between system level and physical level design steps. The leakage power of an IP-block increases with its temperature which is dependent on the SoC's floorplan due to thermal diffusion. We have observed that different floorplans of the same SoC can have up to 3X difference in leakage power. Hence the system designer needs to be aware of this design space between floorplans and leakage power. We propose a leakage aware exploration (LAX) framework which enables the system designer to create this design space early in the design cycle and provides an opportunity to make changes in the system design. We show the size of the design space generated by applying LAX on ten industrial SoC designs from Freescale Semiconductor Inc. and observe that the leakage power can vary by as much as 190% for 65% difference in the inactive area.

关键词： Space exploration system-on-a-chip Intellectual property Space technology Energy consumption system-level design Manufacturing Temperature dependence Power generation Aerospace industry

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Demand paging for OneNANDTM Flash eXecute-in-place

Demand paging for OneNANDTM Flash eXecute-in-place

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Yongseok Choi Eui-Young Chung Naehyuck Chang Sung Woo Chung Chanik Park Yongsoo Joo Seoul National University Korea Yonsei University Korea Samsung Electronics Korea Korea University Korea

NAND flash memory can provide cost-effective secondary storage in mobile embedded systems, but its lack of a random access capability means that code shadowing is generally required, taking up extra RAM space. Demand paging with NAND flash memory has recently been proposed as an alternative which requires less RAM. This scheme is even more attractive for OneNAND flash, which consists of a NAND flash array with SRAM buffers, and supports eXecute-ln-Place (XIP), which allows limited random access to data on the SRAM buffers. We introduce a novel demand paging method for OneNAND flash memory with XIP feature. The proposed on-line demand paging method with XIP adopts finite size sliding window to capture the paging history and thus predict future page demands. We particularly focus on non-critical code accesses which can disturb real-time code. Experimental results show that our method outperforms conventional LRU-based demand paging by 57% in terms of execution time and by 63% in terms of energy consumption. It even beats the optimal solution obtained from MIN, which is a conventional off-line demand paging technique by 30% and 40% respectively.

关键词： Random access memory Embedded system Read-write memory Energy consumption Memory management Algorithm design and analysis Permission system-on-a-chip Decoding User interfaces

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Energy minimization for real-time systems with (m, k)-guarantee

Energy minimization for real-time systems with (<i>m</i>, <i...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Niu, Linwei Quan, Gang Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

Energy consumption and quality of service (QoS) are two primary concerns in the development of today's pervasive computing systems. While most of the current research in energy-aware real-time scheduling has been focused on hard real-time systems, a large number of practical applications and systems exhibit more soft real-time nature. In this paper, we study the problem of minimizing energy for soft real-time systems while providing a QoS guarantee. The QoS requirements are deterministically quantified with the (m, k)-constraints, which require that at least m out of any k consecutive jobs of a task meet their deadlines. In this paper, we propose a hybrid approach to achieve the dual goals of QoS guarantee and energy minimization. We first present the necessary and sufficient schedulability conditions for the static mandatory/optional workload partitioning. Then, we propose to dynamically vary the statically defined mandatory/optional partitions to accommodate dynamic run-time variations while minimizing the energy consumption. The experimental results demonstrate that our proposed techniques outperform previous work significantly in terms of both the energy savings and achieved QoS.

关键词： dynamic volage scaling (DVS) earliest deadline first (EDF) embedded system quality of service (QoS) real-time scheduling

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Cutting across layers of abstraction:: removing obstacles from the advancement of embedded systems

Cutting across layers of abstraction:: removing obstacles fr...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Krisztian Flautner ARM Limited

Silicon technology evolution over the last four decades has yielded an exponential increase in integration densities with steady improvements of performance and power consumption at each technology generation. This steady progress has created a sense of entitlement for the riches that future process generations would bring. Today, however, classical process scaling seems to be dead and living up to technology expectations requires continuous innovation at many levels, which comes at steadily progressing implementation and design costs. Solutions to problems need to cut across layers of abstractions and require coordination between software, architecture and circuit features. Heterogeneous multiprocessor clusters are increasingly used to deliver the required compute power for high-end applications. Heterogeneity ensures that the necessary processing power can be delivered at high levels of efficiency at reasonable implementation cost, while the use of processors endow these systems with large degrees of flexibility. One of the key challenges with these systems is system-level programming. Traditional compiler technologies are strong at programming individual cores but leave the task of parallelization to a team of experts. The first part of this talk will describe the coupling of the compiler to the system architecture on a multi-core signal-processing cluster and illustrate how compiler technology can enable the writing of portable parallel programs for it using little more than C. As claimed above, close coupling of abstraction layers can be beneficial. This can also be illustrated at the microarchitecture - circuit boundary. The second part of the talk will describe a prototype microarchitecture which is designed explicitly to deal with issues such as silicon variation and soft errors. These features in return enable system designers to focus on the typical-case performance of their implementations without having to be over-constrained by worst-case conditions.

关键词： Embedded system Program processors Silicon Costs Circuits Microarchitecture Energy consumption Power generation Technological innovation Computer architecture

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A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control

A buffer-sizing algorithm for networks on chip using TDMA an...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Andrei Ruadulescu Kees Goossens Giovanni De Micheli Srinivasan Murali Martijn Coenen Philips Research Eindhoven The Netherlands CSL Stanford University Stanford USA LSI Switzerland LSI EPFL Switzerland

When designing a system-on-chip (SoC) using a network- on-chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power consumption is due to the buffers in the network interfaces (NIs) needed to decouple computation from communication. Having such a decoupling prevents stalling of IP blocks due to the communication interconnect. The size of these buffers is especially important in real-time systems, as there they should be big enough to obtain predictable performance. To ensure that buffers do not overflow, end- to-end flow-control is needed. One form of end-to-end flow- control used in NoCs is credit-based flow-control. This form places additional requirements on the buffer sizes, because the flow-control delays need to be taken into account. In this work, we present an algorithm to find the minimal decoupling buffer sizes for a NoC using TDMA and credit- based end-to-end flow-control, subject to the performance constraints of the applications running on the SoC. Our experiments show that our method results in a 84% reduction of the total NoC buffer area when compared to the state-of- the art buffer-sizing methods. Moreover, our method has a low run-time complexity, producing results in the order of minutes for our experiments, enabling quick design cycles for large SoC designs. Finally, our method can take into account multiple usecases running on the same SoC.

关键词： Network-on-a-chip Time division multiple access Communication system control system-on-a-chip Energy consumption Silicon Design optimization Network interfaces Computer interfaces Computer networks

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A codesign Tool for High Level Systhesis of Vision Models on FPL

A Codesign Tool for High Level Systhesis of Vision Models on...

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international conference on Field Programmable Logic and Applications

作者： Antonio Martinez Leonardo Reynery Francisco Pelayo Christian Morillas Samuel Romero Department of Computing Technology University of Alicante Spain Department of Electronics Polytechnic of Torino Italy Department of Computer Engineering University of Granada Spain Department of Computer Sciences University of Jaen Spain

This paper presents a synthesis tool for the automatic translation and optimization of bioinspired vision models into a FPL implementation. The software allows functional simulation and high level specification of the model, and produces a data-flow model using VHDL, which is synthesizable with different lower-level synthesis tools and for various FPGA technologies. The proposed design platform extends the features of the codesign environment CodeSimulink for implementing visual processing systems, starting from purely functional specifications. An optimization strategy based on the calculation of the Pareto front is also introduced to perform a multi-objective minimization of both, the circuit area and the root mean square of the computation error. Performance measurements for the FPL implementation of an example retina-like vision model on a FPGA-based PCI board are provided

关键词： Mathematical model Computer vision Field programmable gate arrays Computational modeling Power system modeling hardware Real time systems Filters Design engineering Knowledge engineering

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international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004

International conference on hardware/software codesign and s...

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Second IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004

ISBN: (纸本)1581139373

The proceedings contain 45 papers from the international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004. The topics discussed include: future challenges in embedded systems;dual-pipeline heterogeneous ASIP design;hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis;memory accesses management during high level synthesis;benchmark-based design strategies for single chip heterogeneous multiprocessors;dynamic overlay of scratchpad memory for energy minimization;power-performance trade-offs for reconfigurable computing;and facilitating reuse in hardware models with enhanced type inference.

关键词： Data storage equipment

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international conference on hardware/software codesign and system synthesis

International Conference on Hardware/Software Codesign and S...

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international conference on hardware/software codesign and system synthesis (CODES)

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