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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

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Comparing the size of .NET applications with native code

Comparing the size of .NET applications with native code

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Erven Rohou Roberto Costa STMicroelectronics Manno Switzerland

Byte-code based languages are slowly becoming adopted in embedded domains because of improved security and portability. Another potential reason for their adoption is the reputation for smaller code size than native. This is critical in contexts in which a small memory footprint is crucial to reduce production costs. This paper compares the code size of applications compiled for .NET framework with the same natively compiled for various processors. The paper shows that the assumption of an impressive code size reduction is not reachable and it suggests that the adoption of such languages in embedded contexts be justified by additional arguments. The paper also studies the reasons for this and it compares with the compression ratios achievable for various applications through alternative techniques.

关键词： Java Computer languages Libraries ISO standards Security Runtime environment Application software Computer aided manufacturing Permission Yarn

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hardware/software partitioning of software binaries: a case study of H.264 decode

Hardware/software partitioning of software binaries: a case ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Gordon McGregor Brian Einloth Frank Vahid Greg Stitt Department of Computer Science and Engineering University of California Riverside USA Center for Embedded Computer Systems University of California Irvine USA Freescale Semiconductor Inc. USA

We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application's binary are competitive with partitioning at the C source code level. While such competitiveness has been shown previously for standard benchmark suites involving smaller or unoptimized applications, the case study instead focuses on a complete 16,000-line highly-optimized commercial-grade application, namely an H.264 video decoder. The several month study revealed that binary partitioning was indeed competitive, achieving nearly identical 2.5x speedups as source level partitioning, compared to a standard microprocessor. Furthermore, the study revealed that several simple C-level coding modifications, including pass by value-return, function specialization, algorithmic specialization, hardware-targeted reimplementation, global array elimination, hoisting and sinking of error code, and conversion to explicit control flow, could lead to improved application speedups approaching 7x for both source level and binary level partitioning.

关键词： hardware Decoding Microprocessors Embedded software Field programmable gate arrays Application software software performance Kernel Partitioning algorithms Embedded system

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Dynamic phase analysis for cycle-close trace generation

Dynamic phase analysis for cycle-close trace generation

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Rajesh Gupta Brad Calder Jeremy Lau Cristiano Pereira Department of Computer Science and Engineering University of California San Diego USA

For embedded system development, several companies provide cross-platform development tools to aid in debugging, prototyping and optimization of programs. These are full system emulation systems that can emulate the final binary to be run on the real board, its operating system and devices. Many of these emulation systems do not provide cycle level information due to the time consuming nature of cycle accurate *** this paper we propose a method to provide Cycle-Close Traces of cycle-level statistics for the complete execution of the program in orders of magnitude less time than performing full cycle accurate simulation, with an average error of 3.2%. Our approach uses dynamic phase analysis to generate targeted cycle-close simulation samples. Detailed simulation results for these samples are used to produce fast cycle-close traces during a program's execution, so the user can also watch, pause and debug the currently executing code and its corresponding architecture performance characteristics at any point during execution.

关键词： Analytical models Emulation software debugging software performance Embedded system Operating systems hardware Permission Computer science Design engineering

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Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design

Service dependency graph: an efficient model for hardware/so...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Ahmed Amine Jerraya Frederic Rousseau Aimen Bouchhima Mohamed-wassim Youssef Arnaud Grasset Wander Cesario Lobna Kriaa Adriano Sarmento SLS Group TIMA Laboratory Grenoble France

Complex systems-on-chip are designed by interconnecting pre-designed hardware (HW) and software (SW) components. During the design cycle, a global model of the SoC may be composed of HW and SW models at different abstraction levels. Designing HW/SW interfaces to interconnect SoC components is a source of design bottlenecks. This paper describes a service-based model enabling systematic design and co-simulation of HW/SW interfaces for SoC design. This model, called Service dependency graph (SDG) allows modeling of complex and application-specific interfaces. We present also a model generator that can automatically build HW/SW interfaces based on service and resource requirements described by the SDG. This approach has been applied successfully on the design of an MPEG-4 encoder. Additionally the SDG seems to be an excellent intermediate representation for the design automation of HW/SW interfaces.

关键词： hardware Middleware Costs Design automation Time to market Laboratories Laser sintering MPEG 4 Standard Computer aided instruction Computer interfaces

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A power estimation methodology for systemC transaction level models

A power estimation methodology for systemC transaction level...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Vijay Narayanan Ing-chao Lin Nagu Dhanwada IBM Electronic Design Automation Systems and Technology Group Hopewell Junction NY USA Department of Computer Science Pennsylvania State University University Park PA USA

Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With the presence of complex cores in current day embedded system-on-chip devices, the problem of complete system level power estimation is gaining significance. Transaction level models for SoCs are gaining increasing attention with emerging architectural modeling standards like systemC. In this paper we present a methodology for performing system power estimation for different scenarios or applications being executed on these transaction level models. We describe techniques and a setup for transaction level power characterization, and an approach to augment systemC transaction level models to perform transaction level power estimation. We also present experimental results to validate the accuracy and speed of our approach.

关键词： Power system modeling Integrated circuit modeling Energy consumption Frequency Bandwidth Embedded software Computer architecture State estimation Computer science system-on-a-chip

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Enhanced code density of embedded CISC processors with echo technology

Enhanced code density of embedded CISC processors with echo ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Mauricio Breternitz Herbert Hum Ramesh Peri Jay Pickett Youfeng Wu INTEL Research Laboratory Santa Clara CA USA Low Power Microprocessor Laboratory INTEL Research Laboratory Santa Clara CA USA Compiler Laboratory INTEL Research Laboratory Santa Clara CA USA

Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance loss. In this paper, we develop an algorithm that utilizes a set of novel variable length Echo instructions and evaluate its effectiveness for IA32 binaries. Our experiments show that IA32 processor equipped with Echo instructions is capable of achieving a similar code density as the THUMB extension in the ARM instruction set with significantly lower performance penalty.

关键词： Thumb Performance loss Reduced instruction set computing Program processors Costs Design optimization Optimizing compilers Embedded system Permission Microprocessors

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Using minimal minterms to represent programmability

Using minimal minterms to represent programmability

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Kurt Keutzer Scott J. Weber Electronics Research Laboratory University of California Berkeley USA

We address the problem of formally representing the programmability of a system. We define the programmability of a system as the set of valid execution paths that can be configured statically by software. We formally represent this programmability as a Boolean function. From this representation, we extract a subset of on-set minterms that we call minimal minterms. We prove that these minimal minterms represent the set of smallest schedulable atomic actions of the system, and that we can use a special generator relation to determine if subsets of these actions can be executed in parallel. We also prove that given an arbitrary Boolean function we can extract the minimal minterms and recreate the entire on-set by applying the generator relation to every element of the power set of the set of minimal minterms. Thus, the minimal minterms represent the complete instruction set supported by the system, and the generator relation represents the inherent parallelism among the instructions. Furthermore, we automatically generate the required software development tools and hardware implementation from this representation of programmability. Finally, we show that we can efficiently compute the minimal minterms and apply the generator relation to verify parallel executions on interesting data path systems.

关键词： Boolean functions Instruction sets Scheduling Computer aided instruction Power generation Parallel processing Programming hardware Data mining Algorithm design and analysis

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FlexPath NP: a network processor concept with application-driven flexible processing paths

FlexPath NP: a network processor concept with application-dr...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Andreas Herkersdorf Thomas Wild Rainer Ohlendorf Munich University of Technology Munich Germany

In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via different, optimized processing paths through the NP. Packets with well understood, relatively simple processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP performance and throughput are improved compared to conventional NP architectures. We present analytical performance estimations to quantify the performance advantage of FlexPath (expressed as available CPU instructions for each packet traversing the CPUs) and introduce a platform-based system on Programmable Chip (SoPC) based architecture which implements the FlexPath NP concept.

关键词： hardware Throughput Very large scale integration Virtual private networks DSL Computer architecture Permission Performance analysis Coprocessors Network interfaces

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SOMA: a tool for synthesizing and optimizing memory accesses in ASICs

SOMA: a tool for synthesizing and optimizing memory accesses...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Seth Copen Goldstein Tiberiu Chelcea Tobias Bjerregaard Girish Venkataramani Carnegie Mellon University Pittsburgh USA TU Denmark Lyngby Denmark

Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the MAN architecture. Depending on the parallelism profile, the MAN may be optimized for latency, throughput or both. The optimized MAN is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance.

关键词： Network synthesis Delay Integrated circuit synthesis Large-scale systems Application specific integrated circuits High level synthesis Concurrent computing Throughput hardware design languages Libraries

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A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications

A system-level methodology for fully compensating process va...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： H. Wang M. Miranda F. Lobmaier F. Catthoor A. Papanikolaou IMEC vzw Leuven Belgium Katholieke Universiteit Leuven Leuven Belgium

Process variability is an emerging problem that is becoming worse with each new technology node. Its impact on the performance and energy of memory organizations is severe and degrades the system-level parametric yield. In this paper we propose a broadly applicable system-level technique that can guarantee parametric yield on the memory organization and which minimizes the energy overhead associated to variability in the conventional design process. It is based on offering configuration capabilities at the memory-level and exploiting them at the system-level. This technique can decrease by up to a factor of 5 the energy overhead that is introduced by state-of-the-art process variability compensation techniques, including statistical timing analysis. In this way we obtain results close to the ideal nominal design again.

关键词： Timing Energy consumption Degradation Delay Process design Integrated circuit yield Robustness Runtime Permission Control systems

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