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Novel architecture for loop acceleration: a case study

Novel architecture for loop acceleration: a case study

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sri Parameswaran Newton Cheung Seng Lin Shee School of Computer Science and Engineering University of New South Wales Sydney Australia National Information and Communications Technology Australia NICTA Sydney Australia VaST Systems Technology Corporation Sydney Australia

In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this architecture. To illustrate the advantages of this approach, we investigate a JPEG encoding algorithm and accelerate one of its loop by implementing it in a coprocessor. We contrast the acceleration by implementing the critical segment as two different coprocessors and a set of customized instructions. The two different coprocessor approaches are: a high-level synthesis (HLS) approach; and a custom coprocessor approach. The HLS approach provides a faster method of generating coprocessors. We show that a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, compared to 1.58x for the HLS approach and 1.33x for the customized instruction approach compared with just the main processor. Respective energy savings within the loop are 57%, 28% and 19%.

关键词： Acceleration Coprocessors Application specific processors Australia High level synthesis Delay Parallel processing Pipeline processing Computer architecture Energy consumption

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Performance and power analysis of computer systems

Performance and power analysis of computer systems

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Trevor Mudge Bredt Family Professor of Engineering University of Michigan Ann Arbor USA

This tutorial will present an overview of techniques for architectural-level performance and power analysis of computer systems. It starts with a discussion of metrics for both performance and power, followed by an overview of some widely used benchmarks including SPEC, Mediabench, and MiBench. It then illustrates the use of these benchmarks with some published performance results. After this initial overview, the tutorial will focus on a discussion of architectural simulators to measure performance and *** simulators model systems on a (clock) cycle-by-cycle basis. Their operation will be illustrated with two popular examples: SimpleScalar and M5. Besides performance analysis, these simulators can be extended to include power estimation. Full simulations of complete applications can be extremely time consuming. The tutorial will explain how sampling techniques can be used to reduce simulation time. Finally, it will conclude with a discussion on the accuracy that can be expected from architectural simulators.

关键词： Performance analysis Power engineering computing Power engineering and energy Power measurement Power system modeling Clocks Analytical models Sampling methods Cities and towns

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Shift buffering technique for automatic code synthesis from synchronous dataflow graphs

Shift buffering technique for automatic code synthesis from ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Nikil Dutt Soonhoi Ha Hyunok Oh CECS University of California Irvine CA USA School of EECS Seoul National University Seoul South Korea

This paper proposes a new efficient buffer management technique called shift buffering for automatic code synthesis from synchronous dataflow graphs (SDF). Two previous buffer management methods, linear buffering and modulo (or circular) buffering, assume that samples are queued in the arc buffers in the arrival order and are accessed by moving the buffer indices. But both methods have significant overhead for general multi-rate systems: the linear buffering method requires large size buffers and the modulo buffering method needs run-time overhead of buffer index computation. The proposed shift buffering method shifts samples rather than moving buffer indices. We develop optimal shift buffering algorithms to minimize the number of shifted samples. Our experimental results show that the proposed algorithm saves up to 90% of performance overhead while requiring the same amount of buffer memory as modulo buffering. Considering the sample copy overhead, shift buffering is applicable when memory size is more crucial than performance overhead, and the shifting overhead is less than the modulo addressing overhead. Another advantage of the shift buffering technique is that it supports the library code written with the linear buffering assumption, which is practically more important.

关键词： Signal processing algorithms Runtime Application software Embedded system software libraries software design Pipelines Signal design Digital signal processing Signal synthesis

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Power optimization for universal hash function data path using divide-and-concatenate technique

Power optimization for universal hash function data path usi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Ramesh Karri Bo Yang Department of Electrical and Computer Engineering Polytechnic University Brooklyn NY USA

We present an architecture level low power design technique called divide-and-concatenate for universal hash functions based on the following observations: (i) the power consumption of a w-bit array multiplier and associated universal hash data path decreases as O(w4) if its clock rate remains constant. (ii) two universal hash functions are equivalent if they have the same collision probability property. In the proposed approach we divide a w-bit data path (with collision probability 2-w) into two/four w/2-bit data paths (each with collision probability 2-w/2) and concatenate their results to construct an equivalent w-bit data path (with a collision probability 2-w). A popular low power technique that uses parallel data paths saves 62.10% dynamic power consumption incurring 102% area overhead. In contrast, the divide-and-concatenate technique saves 55.44% dynamic power consumption with only 16% area overhead.

关键词： hardware Energy consumption Clocks Design optimization Computer architecture Authentication Iterative algorithms Power system reliability Arithmetic Logic design

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Future wireless convergence platforms 05

Future wireless convergence platforms

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Mayan Moudgill Michael Schulte Stamatis Vassiliadis Daniel Iancu Gary Nacer Michael Samori Sanjay Jintukar Stuart Stanley Tanuj Raja John Glossner Sandbridge Technologies Inc. White Plains NY USA Sandbridge Technologies Inc. White Plains NY

ISBN: (纸本)9781595931610

As wireless platforms converge to multimedia systems, architectures must converge to support voice, data, and video applications. From a processor architecture perspective, support for signal processing (both audio and video), control code, and Java execution will be required in a convergent device. Traditionally, wireless communications systems have been implemented in hardware. Convergent devices must be able to roam seamlessly across multiple communications systems. To avoid excessive hardware costs, a software Defined Radio (SDR) approach offers a programmable and dynamically reconfigurable method of reusing hardware to implement physical layer processing. In this paper, we discuss trends in wireless platforms which are inherently convergence platforms. We also present the Sandbridge state-of-the-art example platform that supports both communications and multimedia applications processing. The architecture efficiently executes Java, Digital Signal Processing (DSP), and control code. Architectural features that reduce power dissipation and enable real-time processing are described. All of the communications and multimedia processing is executed completely in software without specialized hardware support. The processor is programmed in C with supercomputer-class compiler support for automatic vectorization, multithreading, and DSP semantic analysis.

关键词： Convergence hardware Digital signal processing Computer architecture Communication system control Java Multimedia communication Multimedia systems Video signal processing Wireless communication

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Satisfying real-time constraints with custom instructions

Satisfying real-time constraints with custom instructions

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Tulika Mitra Pan Yu School of Computing National University of Singapore Singapore

Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application of instruction-set extensions to meet timing constraints in real-time embedded systems. In order to satisfy real-time constraints, the worst-case execution time (WCET) of a task should be reduced as opposed to its average-case execution time. Unfortunately, existing custom instruction selection techniques based on average-case profile information may not reduce a task's WCET. We first develop an Integer Linear Programming (ILP) formulation to choose optimal instruction-set extensions for reducing the WCET. However, ILP solutions for this problem are often too expensive to compute. Therefore, we also propose an efficient and scalable heuristic that obtains quite close to the optimal results. Experiment results indicate that suitable choice of custom instructions can reduce the WCET of our benchmark programs by as much as 42% (23.5% on an average).

关键词： Real time systems Embedded system Frequency Computer aided instruction Permission Processor scheduling Clocks Timing Integer linear programming Algorithm design and analysis

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A design flow for an H.264 embedded video encoder

A design flow for an H.264 embedded video encoder

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ITI international conference on Information and Communications Technology (ICICT)

作者： I. Amer W. Badawy G. Jullien Advanced Technology Information Processing Systems ATIPS Calgary AB Canada

hardware/software codesign is a rapidly-growing research area branching from hardware synthesis. The purpose of codesign is to facilitate the design of small embedded systems, that is, those consisting of a microprocessor, for which software is required, in addition to one or more semi-custom ASICs or FPGAs. In this paper, a design flow of an H.264 HW/SW digital video encoder is introduced. A design example of a hardware 4times4 DCT-like transform and quantization block integrated with the H.264 software reference model is described

关键词： hardware Quantization Video coding Embedded system Video compression software performance Embedded software Application software Robustness MPEG 4 Standard

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High-level synthesis for large bit-width multipliers on FPGAs: a case study

High-level synthesis for large bit-width multipliers on FPGA...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： James P. Davis Duncan A. Buell Siddhaveerasharan Devarkal Gang Quan Department of Computer Science and Engineering University of South Carolina Columbia SC USA

In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and/or noisy channels in networking and multimedia applications. The design space for these circuits is very large when integer multiplication on large operands is carried out hierarchically. In this paper, we explore automated synthesis of high bit-width unsigned integer multiplier circuits by defining and validating an estimator function used in search and analysis of the design space of such circuits. We focus on analysis of a hybrid hierarchical multiplier scheme that combines the throughput advantages of parallel multipliers and the resource cost-effectiveness of serial ones. We present an analytical model that rapidly predicts timing and resource usage for selected model candidates. We evaluate the estimator model in the design of a practical application, a 256-bit elliptic curve adder implemented on a Xilinx FPGA fabric. We show that our estimator allows implementation of fast, efficient circuits, where resultant designs provide order-of-magnitude performance improvements when compared with that of software implementations on a high performance computing platform.

关键词： High level synthesis Field programmable gate arrays Elliptic curve cryptography Error correction Circuit noise Circuit synthesis Network synthesis Throughput Analytical models Timing

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A cycle-accurate compilation algorithm for custom pipelined datapaths

A cycle-accurate compilation algorithm for custom pipelined ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Daniel Gajski Mehrdad Reshadi Center for Embedded Computer Systems CECS University of California Irvine CA USA

Traditional high level synthesis (HLS) techniques generate a datapath and controller for a given behavioral description. The growing wiring cost and delay of today technologies require aggressive optimizations, such as interconnect pipelining, that cannot be done after generating the datapath and without invalidating the schedule. On the other hand, the increasing manufacturing complexities demand approaches that favor design for manufacturability (DFM).To address these problems we propose an approach in which the datapath of the architecture is fully allocated before scheduling and binding. We compile a C program directly to the datapath and generate the controller. We can support the entire ANSI C syntax because the datapath can be as complex as the datapath of a processor. Since there is no instruction abstraction in this architecture we call it No-Instruction-Set-Computer (NISC). As the first step towards realization of a NISC-based design flow, we present an algorithm that maps an application on a given datapath by performing scheduling and binding simultaneously. With this algorithm, we achieved up to 70% speedup on a NISC with a datapath similar to that of MIPS, compared to a MIPS gcc compiler. It also efficiently handles different datapath features such as pipelining, forwarding and multi-cycle units.

关键词： Job shop scheduling High level synthesis Pipeline processing Manufacturing Processor scheduling Wiring Cost function Delay Algorithm design and analysis Scheduling algorithm

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Memory access optimizations in instruction-set simulators

Memory access optimizations in instruction-set simulators

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Prabhat Mishra Mehrdad Reshadi Center for Embedded Computer Systems (CECS) University of California Irvine Irvine CA USA Computer and Information Science and Engineering University of Florida Gainesville FL USA

Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simulators are widely used in embedded systems design. One of the key performance bottlenecks in interpretive simulation is the instruction and data memory access translation between host and target machines. The simulators must maintain and update the status of the simulated processor including memory and register values. A major challenge in the simulation is to efficiently map the target address space to the host address space. This paper presents two optimization techniques that aggressively utilize the spatial locality of the instruction and data accesses in interpretive simulation: signature based address mapping for optimizing general memory accesses; and incremental instruction fetch for optimizing instruction accesses. To demonstrate the utility of this approach we applied these techniques on SimpleScalar simulator, and obtained up to 30% performance improvement. Our techniques complement the recently proposed optimizations (JIT-CCS [1] and IS-CS [2]) and further improve the performance (up to 89%) on ARM7 and Sparc processors.

关键词： Decoding Computational modeling Runtime Computer aided instruction Embedded computing Embedded system Permission Computer simulation Information science Process design

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