检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

822 篇 会议
31 篇 期刊文献

馆藏范围

853 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

409 篇 工学
- 393 篇 计算机科学与技术...
- 319 篇 软件工程
- 82 篇 电子科学与技术（可...
- 60 篇 电气工程
- 43 篇 信息与通信工程
- 39 篇 控制科学与工程
- 9 篇 动力工程及工程热...
- 7 篇 机械工程
- 7 篇 光学工程
- 5 篇 材料科学与工程（可...
- 5 篇 建筑学
- 4 篇 土木工程
- 4 篇 安全科学与工程
- 3 篇 仪器科学与技术
- 3 篇 化学工程与技术
- 3 篇 航空宇航科学与技...
- 2 篇 力学（可授工学、理...
- 2 篇 环境科学与工程（可...
- 2 篇 生物医学工程（可授...
99 篇 理学
- 58 篇 数学
- 37 篇 系统科学
- 17 篇 物理学
- 8 篇 统计学（可授理学、...
- 2 篇 化学
55 篇 管理学
- 45 篇 管理科学与工程(可...
- 15 篇 工商管理
- 13 篇 图书情报与档案管...
5 篇 法学
- 4 篇 社会学
- 1 篇 法学
3 篇 经济学
- 3 篇 应用经济学
1 篇 医学
1 篇 艺术学

主题

167 篇 hardware
94 篇 computer archite...
76 篇 embedded system
58 篇 application soft...
56 篇 permission
50 篇 embedded systems
47 篇 system-on-a-chip
45 篇 software
44 篇 algorithm design...
42 篇 computational mo...
41 篇 energy consumpti...
41 篇 field programmab...
35 篇 costs
34 篇 system-on-chip
32 篇 space exploratio...
30 篇 high level synth...
29 篇 system-level des...
27 篇 timing
26 篇 delay
25 篇 embedded softwar...

机构

8 篇 center for embed...
6 篇 school of comput...
6 篇 arizona state un...
6 篇 center for embed...
6 篇 department of co...
5 篇 school of inform...
5 篇 philips research...
5 篇 univ calif river...
5 篇 institute for in...
5 篇 department of el...
4 篇 department of co...
4 篇 university of er...
4 篇 tu braunschweig
4 篇 university of do...
4 篇 tensilica
4 篇 univ elect sci &...
4 篇 nec laboratories...
4 篇 philips research...
3 篇 integrated signa...
3 篇 east china norma...

作者

10 篇 ogras umit y.
9 篇 sri parameswaran
9 篇 nikil dutt
7 篇 rolf ernst
7 篇 parameswaran sri
7 篇 leupers rainer
6 篇 jiang wei
6 篇 dutt nikil
6 篇 robert p. dick
6 篇 mitra tulika
6 篇 rainer leupers
6 篇 andreas gerstlau...
5 篇 pasricha sudeep
5 篇 gerd ascheid
5 篇 greg stitt
5 篇 jinyu zhan
5 篇 umit y. ogras
5 篇 tei-wei kuo
5 篇 wei jiang
5 篇 yuan-hao chang

语言

850 篇 英文
3 篇 其他
1 篇 中文

检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 853 条记录，以下是681-690 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

An efficient direct mapped instruction cache for application-specific embedded systems

An efficient direct mapped instruction cache for application...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Chuanjun Zhang Computer Science and Electrical Engineering Department University of Missouri Kansas City Kansas City MO USA

Caches may consume half of a microprocessor's total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing cache power consumption and reducing cache misses are important to reduce total energy consumption of embedded systems. Direct mapped caches consume much less power than that of same sized set associative caches but with a poor hit rate on average. Through experiments, we observe that memory space of direct mapped instruction caches is not used efficiently in most embedded applications. We design an efficient cache - a configurable instruction cache that can be tuned to utilize the cache sets efficiently for a particular application such that cache memory is exploited more efficiently by index remapping. Experiments on 11 benchmarks drawn from Mediabench show that the efficient cache achieves almost the same miss rate as a conventional two-way set associative cache on average and with total memory-access energy savings of 30% compared with a conventional two-way set associative cache.

关键词： Embedded system Energy consumption Delta modulation Cache memory Algorithm design and analysis Cities and towns Computer science Clocks Frequency Application specific processors

来源：评论

学校读者我要写书评

暂无评论

Enhancing security through hardware-assisted run-time validation of program data properties

Enhancing security through hardware-assisted run-time valida...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Anand Raghunathan Niraj K. Jha Srivaths Ravi Divya Arora Department of Electrical Engineering Princeton University Princeton NJ USA NEC Laboratories of America Inc. Princeton NJ USA

The growing number of information security breaches in electronic and computing systems calls for new design paradigms that consider security as a primary design objective. This is particularly relevant in the embedded domain, where the security solution should be customized to the needs of the target system, while considering other design objectives such as cost, performance, and power. Due to the increasing complexity and shrinking design cycles of embedded software, most embedded systems present a host of software vulnerabilities that can be exploited by security attacks. Many attacks are initiated by causing a violation in the properties of data ( e.g., integrity, privacy, access control rules, etc.) associated with a "trusted" program that is executing on the system, leading to a range of undesirable *** this work, we develop a general framework that provides security assurance against a wide class of security attacks. Our work is based on the observation that a program's permissible behaviorwith respect to data accesses can be characterized by certain properties. We present a hardware/software approach wherein such properties can be encoded as data attributes and enforced as security policies during program execution. These policies may be application-specific (e.g., access control for certain data structures), compiler-generated (e.g., enforcing that variables are accessed only within their scope), or universally applicable to all programs (e.g., disallowing writes to unallocated memory). We show how an embedded system architecture can support such policies by (i) enhancing the memory hierarchy to represent the attributes of each datum as security tags that are linked to it through its lifetime, and (ii) adding a configurable hardware checker that interprets the semantics of the tags and enforces the desired security policies. We evaluated the effectiveness of the proposed architecture in enforcing various security policies for several embedded benchma

关键词： Data security Runtime Information security Power system security Embedded software Embedded system Access control hardware Costs Data privacy

来源：评论

学校读者我要写书评

暂无评论

Designing real-time H.264 decoders with dataflow architectures

Designing real-time H.264 decoders with dataflow architectur...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Suleyman Sair Youngsoo Kim Department of Electrical and Computer Engineering NC State University USA

High performance microprocessors are designed with general-purpose applications in mind. When it comes to embedded applications, these architectures typically perform control-intensive tasks in a system-on-Chip (SoC) design. But they are significantly inefficient for data-intensive tasks such as video encoding/decoding. Although configurable processors fill this gap by complementing the existing functional units with instruction extensions, their performance lags behind the needs of real-time embedded tasks. In this paper, we evaluate the performance potential of a dataflow processor for H.264 video decoding. We first profile the H.264 application to capture the amount of data traffic among modules. We use this information to guide the placement of H.264 modules in the WaveScalar dataflow architecture. A simulated annealing based placement algorithm produces the final placement aiming to optimize the communication costs between the modules in the dataflow architecture. In addition to outperforming contemporary embedded and customized processors, our simulated annealing guided design shows a speedup of 13% in execution time over the original WaveScalar architecture. With our dataflow design methodology, emerging embedded applications requiring several GOPS to meet real-time constraints can be drafted within a reasonable amount of design time.

关键词： Decoding Computer architecture Design methodology Application software Acceleration Encoding Simulated annealing Permission Microprocessors Control systems

来源：评论

学校读者我要写书评

暂无评论

Improving superword level parallelism support in modern compilers

Improving superword level parallelism support in modern comp...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Manuel Prieto Luis Pinuel F. Catthoor Francisco Tirado Christian Tenllado Departmento Arquitectura de Computadores y Automática Universidad Complutense de Madrid Madrid Spain Micro Electronic Center IMEC Inter University Leuven Belgium

Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology do not allow for an efficient exploitation of the inherent data parallelism available in many signal processing and multimedia applications. In this paper, we have explored the automatic vectorization of embedded applications. In particular, we have focused on algorithms in which the same computations are applied over a set of signals that are being processed simultaneously. Usually this set of signals is represented as a 2D array in which each row is an input signal that has to be filtered in some way. A motivating example, inspired by VoIP processing, illustrates that state-of-the-art vectorizing compilers inefficiently exploit the data parallelism inherent to this kind of applications. One of the main reasons behind this, is that they present inner loops that carry all the dependencies and external loops with strided memory *** propose a modification of the Superword Level Parallelism (SLP) compiler, proposed in [9], that tries to overcome these problems. Experimental results show that our approach clearly outperforms commercial compilers.

关键词： Signal processing algorithms Parallel processing Signal processing Multimedia systems Embedded system Finite impulse response filter Systolic arrays Permission Pervasive computing Microelectronics

来源：评论

学校读者我要写书评

暂无评论

Aggregating processor free time for energy reduction

Aggregating processor free time for energy reduction

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Alex Nicolau Nikil Dutt Eugene Earlie Aviral Shrivastava Center for Embedded Computer Systems School of Information and Computer Science University of California Irvine CA USA Strategic CAD Laboratories Intel Corporation Hudson MA USA

Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the processor stalls, waiting for data from the memory. Processor stall can be used to increase the throughput by temporarily switching to a different thread of execution, or reduce the power and energy consumption by temporarily switching the processor to low-power mode. However, any such technique has a performance overhead in terms of switching time. Even though over the execution of an application the processor is stalled for a considerable amount of time, each stall duration is too small to profitably perform any state switch. In this paper, we present code transformations to aggregate processor free time. Our experiments on the Intel XScale and Stream kernels show that up to 50,000 processor cycles can be aggregated, and used to profitably switch the processor to low-power mode. We further show that our code transformations can switch the processor to low-power mode for up to 75% of kernel runtime, achieving up to 18% of processor energy savings on multimedia applications. Our technique requires minimal architectural modifications and incurs negligible ( < 1%) performance loss.

关键词： Switches Embedded computing Application software Embedded system Algorithm design and analysis Energy consumption Kernel Delay Permission Computer science

来源：评论

学校读者我要写书评

暂无评论

hardware and software architectures for the CELL processor

Hardware and software architectures for the CELL processor

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Michael Day Peter Hofstee Cell Chief Scientist and Cell Synergistic Processor Chief Architect IBM Systems and Technology Group Austin TX USA Cell Chief Software Architect and Distinguished Engineer IBM Systems and Technology Group Austin TX USA

The Cell processor is a first instance of a new family of processors intended for the broadband era. The processors will find early use in game systems (PlayStation3TM), a variety of other consumer electronics applications, a wide variety of embedded applications, and various forms of computational accelerators. Cell is a non-homogeneous multi-core processor, with one POWER processor core (two threads) dedicated to the operating system and other control functions, and eight synergistic processors optimized for compute-intensive *** addresses two of the main limiters to microprocessor performance: increased memory latency, and performance limitations induced by system power limits. Memory latency is addressed by introducing another software-managed level of private "local" memory, in between the private registers and shared system memory. Data is transferred between this local memory and shared memory with asynchronous cache coherent DMA commands, and synergistic processor load and store commands access the local store only. This organization of memory makes it possible for the Cell processor to have over 100 memory transactions in flight at the same time, more than enough to cover memory latency. Power limitations are addressed by two main mechanisms; a non-homogeneous multi-core organization, and an ultra high-frequency design that allows the chip to be operated at 3.2GHz at low *** Cell processor supports many of today's programming models by introducing the concept of heterogeneous tasks or threads. Both Power processor and SPE based threads can be managed by the operating system and effectively utilized by applications starting with the relatively straightforward function offload model to the more complex single source heterogeneous parallel programming model. Cell achieves between one and two orders of magnitude of performance advantage over conventional single-core processors on compute-intensive (32-bit) applications, by permitting progr

关键词： hardware software architecture Yarn Delay Power system modeling Application software Operating systems Computer applications Registers Games

来源：评论

学校读者我要写书评

暂无评论

Blue matter on blue gene/L: massively parallel computation for biomolecular simulation

Blue matter on blue gene/L: massively parallel computation f...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Frank Suits Maria Eleftheriou Mark Giampapa Aleksandr Rayshubskiy Blake Fitch Michael C. Pitman T.J. Christopher Ward Robert S. Germain IBM Thomas J. Watson Research Center Yorktown Heights NY USA IBM Hursley Park Hursley UK

This paper provides an overview of the Blue Matter application development effort within the Blue Gene project that supports our scientific simulation efforts in the areas of protein folding and membrane-protein systems. The design philosophy of the Blue Gene/L architecture relies on large numbers of power efficient nodes (whose technology is derived from the world of embedded microprocessors) to enable packing of many such nodes into a small volume to achieve high performance. In order for an application to exploit the potential of this architecture, the application must scale well to large node counts. Because the scientific goals of the project entail simulating very long time-scales, up to microseconds, strong scaling of a fixed size problem to these large node counts is a requirement. In pursuit of this objective we have considered a variety of parallel decompositions and explored ways to exploit and map algorithms onto the two primary high performance interconnects provided by the Blue Gene architecture, the 3D-torus network and the collective network. Our current version of the application continues to speed up through 4096 nodes and is being used for studies of a protein/lipid system (for which some results have already been published) and for protein folding/unfolding simulations.

关键词： Concurrent computing Computational modeling Biological system modeling Proteins hardware Bonding forces Boundary conditions Microprocessors Permission Supercomputers

来源：评论

学校读者我要写书评

暂无评论

FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals 05

FIDES: an advanced chip multiprocessor platform for secure n...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Masaki Kondo Masato Edahiro Akihisa Ikeno Junji Sakai Hiroaki Inoue System Devices Research Laboratories Kanagawa Japan NEC Informatec Systems Ltd. Takatsu-ku Kawasaki Kanagawa Japan

ISBN: (纸本)9781595931610

We propose a secure platform on a chip multiprocessor, known as FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multi-grained separation mechanisms: coarse-grained processor-level separation of the basic-function domain from other domains for such downloaded applications, medium-grained OS-level separation, and fine-grained process-level separation within SELinux. Four new technologies, which include three enhancements to SELinux, support the FIDES platform: 1) bus filter logic for processor-level separation can be implemented as a small logic, 2) XIP kernels for memory-efficient OS-level separation can reduce memory requirements by 182%, 3) policy separation for enhanced process-level separation can apply policies 2.1 times faster at system boot-up, and 4) dynamic access control can provide secure Inter-Domain Communications (IDCs) with an overhead of only 4% for IDC system calls. We implemented SELinuxes on an ARM-based multiprocessor. Therefore, the best-suited platform to secure next generation mobile terminals is the FIDES platform, which can provide higher security as well as higher performance and lower power consumption on chip multiprocessors leading the current technology trend of microprocessors.

关键词： Logic Linux Filters Kernel Access control Mobile communication Communication system security Power system security Energy consumption Microprocessors

来源：评论

学校读者我要写书评

暂无评论

Performance Evaluation of a Noise Canceller Filter to be used in codesign Techniques

Performance Evaluation of a Noise Canceller Filter to be use...

引用

Eurocon

作者： E.M. de Icaya V. Rodellar V. Peinado V. Garcia A. Diaz C. Gonzalez E.U.I(University School of Computer Science) Universidad Politécnicade Madrid Madrid Spain Madrid Spain (Faculty of Computer Science) of UPM Campus de Montegancedos/n Madrid Spain

codesign techniques allow exploring different design alternatives at the system level specification by means of realizations in hardware and software for each composing blocks, and thus to evaluate the system performance before choosing the final implementation. In this paper the performance estimation in terms of area, time and power dissipation of a noise canceller filter both in software and hardware implementations is presented. The approximation has consisted of the specification of the problem in ANSI C and its transformation through synthesis tools into assembler code for the DSP 56000 microprocessor and into RTL VHDL synthesizable code by means of SPARK (S. Gupta et al., 2003). Also more precise hardware estimation for FPGA's and standard cells is presented

关键词： Noise cancellation Filters hardware software performance system performance Power dissipation Assembly Digital signal processing Microprocessors Sparks

来源：评论

学校读者我要写书评

暂无评论

Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines 05

Enabling unrestricted automated synthesis of portable hardwa...

引用

Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Miljan VuletiĆ Christophe Dubach Laura Pozzi Paolo Ienne Ecole Polytechnique Fédérale de Lausanne (EPFL) Lausanne Switzerland

ISBN: (纸本)9781595931610

The performance of virtual machines (e.g., Java Virtual Machines---JVMs) can be significantly improved when critical code sections (e.g., Java bytecode methods) are migrated from software to reconfigurable hardware. In contrast to the compile-once-run-anywhere concept of virtual machines, reconfigurable applications lack portability and transparent SW/HW interfacing: applicability of accelerated hardware solutions is often limited to a single platform. In this work, we apply a virtualisation layer that provides portable and seamless integration of hardware and software components to a Java Virtual Machine platform, making it capable of accelerating any Java bytecode method by using platform-independent hardware accelerators. The virtualisation layer not only improves portability of accelerated Java bytecode applications, but also supports runtime optimisations and enables unrestricted automated synthesis of arbitrary Java bytecode to hardware. To show the advantages and measure the limited overheads of our approach, we run several accelerated applications (handwritten and synthesised) on a real embedded platform. We also show our synthesis flow and discuss its advanced features fostered by the virtualisation layer.

关键词： accelerator synthesis virtual machine

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共86页 << < 65 66 67 68 69 70 71 72 73 74 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：