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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

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Tutorial: Large-Scale Spiking Neuromorphic Architecture Exploration using SANA-FE

Tutorial: Large-Scale Spiking Neuromorphic Architecture Expl...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： James A. Boyle Mark Plagge Suma G. Cardwell Frances S. Chanc Andreas Gerstlauer The University of Texas at Austin Texas USA Sandia National Laboratories New Mexico USA

ISBN: (数字)9798350356397

ISBN: (纸本)9798350356403

Neuromorphic computing uses brain-inspired concepts to accelerate and efficiently execute a wide range of applications, such as mimicking biological circuits, solving NPhard optimization problems and accelerating machine learning at the edge. In particular, neuromorphic architectures to efficiently execute Spiking Neural Networks (SNNs) have gained popularity. SNNs extend artificial neural networks (ANNs) by encoding information in time as either rates or delays between spiking events, shared between neurons via their weighted connections. SNN-based platforms are event-driven, resulting in naturally sparse, noise-tolerant and power-efficient computation. In this tutorial, we present the state-of-the-art in scalable digital and analog spiking neuromorphic system architectures, and discuss current research trends within the neuromorphic architecture field at the system level. We further introduce our SANA-FE tool for Simulation of Advanced Neuromorphic Architectures for Fast Exploration, which has been developed as part of a collaboration between the University of Texas at Austin and Sandia National Laboratories. SANA-FE allows for modeling and performance-power prediction of different spiking hardware architectures executing SNN applications to support rapid, early system-level design-space exploration, hardware-aware application development and system architecture co-design. The tutorial includes a hands-on component in which SANA-FE’s capabilities are demonstrated and used to perform system design and application mapping case studies.

关键词： Neuromorphic engineering Neurons systems architecture Computer architecture Tutorials Spiking neural networks Predictive models Market research system analysis and design Optimization

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FPGA-Based hardware Optimization and Implementation of YOLOv4-tiny 3

FPGA-Based Hardware Optimization and Implementation of YOLOv...

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3rd international conference on Communications, Information system, and Data Science, CISDS 2024

作者： Wang, Kai Bai, Yanhong Li, Xiaosong Department of Electronic Information Engineering Taiyuan University of Science and Technology Taiyuan030024 China Department of Intelligent Manufacturing Industry Shanxi University of Electronic Science and Technology Linfen041000 China

ISBN: (数字)9781510688322

ISBN: (纸本)9781510688315

To address the challenges associated with the YOLOv4-Tiny algorithm's complex structure, high computational resource requirements, and extensive parameter count-which collectively impede efficient FPGA deployment-we propose a hardware-software co-optimization strategy. This approach replaces the YOLOv4-Tiny backbone with the MobileNetv1 network and integrates the Convolutional Block Attention Module (CBAM) into the enhanced feature extraction network. Channel pruning is applied to streamline the network structure, and weights and biases are quantized to 16-bit fixed-point representations. Compared to the original YOLOv4-Tiny, this optimized network reduces parameters by 40% while retaining nearly identical recognition *** high-level synthesis tools, we generate FPGA IP cores, design a parallel pipelined convolutional architecture, and implement inter-layer blocking between convolutional layers to enhance computational efficiency. This improved algorithm is deployed on a Zynq-7020 FPGA chip. Experimental results show that the optimized algorithm achieves a computational performance of 43.4 GOP/s, offering a speedup of 1.6 to 4.1 times compared to existing studies, with an energy efficiency ratio 4.8 to 10.7 times greater than current implementations. These findings indicate that the proposed strategy significantly improves algorithm deployment efficiency on resource-limited FPGA platforms. © 2025 SPIE.

关键词： High level synthesis

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The Integration and Testing Procedures for the AcubeSAT Nanosatellite's software 20

The Integration and Testing Procedures for the AcubeSAT Nano...

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20th international conference on synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024

作者： Keremidis, Antonios Tzelepis, Stylianos Hatzopoulos, Alkis National Technical University of Athens Greece SpaceDot Greece Aristotle University of Thessaloniki Greece AUTh Electronics Lab Dept. of Electrical and Computer Eng Greece

ISBN: (纸本)9798350351927

The AcubeSAT space mission, a collaborative effort within the Fly Your Satellite! 3 program of the European Space Agency (ESA) Education Office and SpaceDot, features unique payload requirements aimed at exploring the effects of radiation and microgravity on eukaryotic cells in Low Earth Orbit (LEO). To address these specialized needs, custom Printed Circuit Board (PCB)s were developed, bypassing off-the-shelf solutions for greater efficiency of the mission and cost-effectiveness. However, this decision introduced a notable challenge: the development of complex system software to ensure the successful execution of all mission phases and the secure transmission of scientific data back to Earth. In this paper, we report on the status of the development and validation processes for the satellite software in its current state, on custom hardware to ensure mission success. © 2024 IEEE.

关键词： Integration testing

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A High-Speed, Area-Optimized, ROM-Less (Co)Sine Wave synthesis Accelerator 16

A High-Speed, Area-Optimized, ROM-Less (Co)Sine Wave Synthes...

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16th international Symposium on Electronics and Telecommunications, ISETC 2024

作者： Stoica, Florentina-Giulia Calinescu, Alex Enachescu, Marius Electronic Devices Circuits and Architectures University Politehnica of Bucharest Faculty of Electronics Telecommunications and Information Technology Bucharest Romania

ISBN: (纸本)9798350390865

Sine and cosine wave synthesis is utilized for generating sinusoidal-alike values in the digital domain. While this task is handled through software, dedicated hardware like Direct Digital synthesis (DDS) is also available. However, both methods rely on memory resources, such as look-up tables and Read-Only Memories (ROMs), which face latency limitations related to additional memory access times on top of additional Si area. With the advent of real-time arithmetic for sine wave approximation, this paper presents an all-in-one digital module that employs iterative multiply-accumulate (MAC) operations for sine and cosine synthesis, ready to be integrated in systems-on-Chip (SoCs), Field Programmable Gate Arrays (FPGAs), or even standalone ASICs. Compared to ROM-less solutions like Taylor approximation, the proposed architecture achieves 80.80% lower resource utilization, 80.39% reduced propagation delay, and 36.66% higher accuracy in sine and cosine wave approximation, both operating as 32-bit systems with one sample per clock cycle. © 2024 IEEE.

关键词： system-on-chip

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Research on vibration signal processing system based on FPGA

Research on vibration signal processing system based on FPGA

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2024 international conference on Image, Signal Processing, and Pattern Recognition, ISPP 2024

作者： Ning, Keqing Xie, Aoyang Xing, Na Du, Minghua North China University of Technology Jinyuanzhuang Road Shijingshan District Beijing China

ISBN: (纸本)9781510680425

To overcome the limitations of software demodulation in laser vibration measurement, a hardware demodulation scheme based on a field-programmable gate array (FPGA) is designed. The reference signal is synthesized using direct digital frequency synthesis and mixed with the Doppler signal. An orthogonal baseband signal is then generated through Butterworth low-pass filtering. Subsequently, a nonlinear error compensation algorithm is introduced to rectify errors. The CORDIC algorithm is applied for inverse tangent demodulation of the laser signal, while a phase detuning algorithm addresses signal hopping issues. Following data processing, the fast Fourier algorithm is used for time-frequency analysis of the vibration data signal. The proposed algorithm undergoes theoretical analysis and experimental verification, ensuring real-time vibration detection and meeting high precision requirements. This offers a more concise and efficient solution for laser vibration measurement systems. © 2024 SPIE.

关键词： Vibration measurement

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Data Transfer Using AMBA Bus: An Empirical Approach 2

Data Transfer Using AMBA Bus: An Empirical Approach

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2nd international conference on Artificial Intelligence and Machine Learning Applications, AIMLA 2024

作者： Savadatti, Mamta B Vinay, R. Sahil Subbaiah, M.L. Shashank, V. Reddy, Tharugu Jayavardhan New Horizon College of Engineering Dept. of ECE Bengaluru India

ISBN: (纸本)9798350349221

This paper presents an AMBA (Advanced Microcontroller Bus Architecture) based design bridging the Advanced High-performance Bus (AHB) to Advanced Peripheral Bus (APB) bus architecture. The AHB to APB bridge facilitates communication and data transfer between high-performance components connected to the AHB bus and low-speed peripheral devices like UART (Universal Asynchronous Receiver), timer, PIO, etc. Connected to the APB bus within a system-on-Chip (SoC) design. In this paper we have created a synthesizable AHB to APB bridge and testbench design with functional proof in Verilog hardware Descriptive Language. The software tools used are all open source and available on Linux based operating system. Using GtkWave for waveform visualization, Icarus Verilog for RTL (Register-Transfer Level) simulation, and Yosys for synthesis and formal verification, we present a comprehensive methodology for designing, verifying, and validating the AHB to APB bus bridge. We demonstrate the simulation-based verification process, capturing signal waveforms, analyzing bus transactions, and ensuring protocol compliance. © 2024 IEEE.

关键词： system-on-chip

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Research on Intelligent Relic Interpretation system Based on a Large Language Model 24

Research on Intelligent Relic Interpretation System Based on...

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24th IEEE international conference on software Quality, Reliability and Security Companion, QRS-C 2024

作者： Guo, Jingjing Han, Xi Beijing Union University Beijing Key Laboratory of Information Service Engineering Beijing China College of Robotics Beijing Union University Beijing China

ISBN: (纸本)9798350365658

Nowadays, docents are the main force for inheriting and displaying human cultural heritage. However, the experience of visitors largely depends on their knowledge depth and updates. Large language models (LLMs) have demonstrated promising results across various fields due to their robust linguistic intelligence acquired through extensive data training. Nevertheless, training LLMs remains challenging due to their high hardware requirements. How can we integrate a LLM into a relic interpretation system without the need for extensive training? To this end, a solution is proposed by combining a LLM with a private domain database to create an intelligent relic interpretation system. This system encompasses the following functionalities:(1) Speech recognition and synthesis: Users input speech, and the system utilizes speech recognition technology to convert the speech into text. This text is then processed by the LLM, and the model's responses are synthesized into speech output;(2) Professional knowledge explanation: Leveraging a LLM and a private domain database to achieve more accurate and professional responses, compared to simply fine-tuning LLMs, this allows for the application of LLMs in vertical fields without the need for additional training;(3) Private domain database renewal: Two methods for updating the database are used: extracting relevant data from intranet sources and uploading data by professionals. The performance of the system is evaluated through comparison and ablation experiments. The results demonstrate that the system effectively addresses the limitations of traditional relic interpretation methods and introduces novel perspectives for relic interpretation. © 2024 IEEE.

关键词： Speech recognition

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The Implementation of Battery Charging Strategy for IoT Nodes

The Implementation of Battery Charging Strategy for IoT Node...

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29th international conference on Parallel and Distributed Computing (Euro-Par)

作者： Rajkovic, Petar Aleksic, Dejan Jankovic, Dragan Univ Nis Fac Elect Engn Aleksandra Medvedeva 14 Nish Serbia Univ Nis Fac Sci & Math Dept Phys Nish Serbia

ISBN: (纸本)9783031488023;9783031488030

The Internet of Things (IoT) nodes dedicated to off-grid usage must fully rely on their battery power for continuous operation. In that sense battery charging process design is one of the focal points for the complete system design. Nowadays, battery charging, for such devices, usually relies on solar power which is not, unfortunately, the source of constant energy. Both environmental and constructive elements could easily make a negative impact on the charging process and reduce the amount of collected energy. Furthermore, if the IoT nodes are in hazardous areas, they are less accessible, and the value of effective battery management is even higher. The requirements for the battery charging process implementation are considered as opposite - on one hand, the requirement is to run charging with the lowest possible frequency and not up to 100%, and on the other hand, the battery should always have enough energy to maintain regular operation. In this research, we present the structure of the custom-developed IoT node based on the ECS32 system-on-a-chip dedicated to operating in remote industrial areas, and with an accent of its battery charging routine. The current routine is based on a standard thresholds approach and improved by including consumption estimates for the predefined periods. This paper presents the first results and should pave the ground for further upgrades. In addition, the comparison with state-of-the-art charging approaches is presented, as the guidelines for future work.

关键词： Internet of things resource awareness industry 4.0 hardware-software codesign

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16-Bit SABP: Quasi-Stochastic Data Representation Unit for AI hardware Using FPGA 37

16-Bit SABP: Quasi-Stochastic Data Representation Unit for A...

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37th IEEE international system-on-Chip conference, SOCC 2024

作者： Abdelfattah, Marwan A. Ahmed, Hossam O. Abdelghany, Mohamed A. German University in Cairo Computer Science and Engineering Department Egypt American University of the Middle East College of Engineering and Technology Egaila54200 Kuwait German University in Cairo Electronics and Engineering Department Egypt

ISBN: (纸本)9798350377569

Efficient data representation is a cornerstone in various domains such as Artificial Intelligence (AI), image processing, and video processing. Discovering the optimal data representation is key to enhancing interfacing, reducing computational complexity, and minimizing power consumption, particularly for digital hardware platforms. This paper presents three modifications to the state-of-the-art 10-bit Bent-Pyramid system, known for its quasi-stochastic data representation. We propose an upgrade to a 16-bit Bent Pyramid (BP), aiming to achieve a higher dynamic range resolution. These proposed three phases are the 16-bit Bent Pyramid (BP), the 16-bit Shifted Bent Pyramid (SBP), and the 16-bit Shifted Asserted Bent Pyramid (SABP). Throughout these modification stages, the latest version of BSA-BP effectively decreases the maximum multiplication error to an impressive 8.2% in a single multiplication instance, as opposed to 9% in two multiplication instances observed in the state-of-the-art research. The SABP architecture has been designed using VHDL, and the targeted FPGA was the Intel Cyclone V 5CGXFC9D6F27C7 chip. According to the synthesis findings of the Intel Quartus Prime software, the maximum operating frequency is 969.93 MHz, and there is only 7.02 mW of total thermal power dissipation per SABP block. The suggested 16-bit SABP demonstrated a lower maximum error rate drop of 8. 8 9% and 7. 8 6%, respectively, in contrast to the cutting-edge 10bit BP and the 16-bit SC. © 2024 IEEE.

关键词： Stochastic systems

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Quantum hardware Roofline: Evaluating the Impact of Gate Expressivity on Quantum Processor Design

Quantum Hardware Roofline: Evaluating the Impact of Gate Exp...

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Quantum Computing and Engineering (QCE), IEEE international conference on

作者： Justin Kalloor Mathias Weiden Ed Younis John Kubiatowicz Bert De Jong Costin Iancu Department of Electrical Engineering and Computer Science University of California Berkeley Computational Research Division Lawrence Berkeley National Laboratory

ISBN: (数字)9798331541378

ISBN: (纸本)9798331541385

The design space of current quantum computers is expansive, with no obvious winning solution, leaving practitioners with a crucial question: “What is the optimal system configuration to run an algorithm?” This paper explores hardware design trade-offs across NISQ systems to better guide algorithm and hardware development. Algorithmic workloads and fidelity models drive the evaluation to appropriately capture architectural features such as gate expressivity, fidelity, and crosstalk. As a result of our analysis, we extend the criteria for gate design and selection from only maximizing average fidelity to a more comprehensive approach that additionally considers expressivity with respect to algorithm structures. A custom synthesis-driven compilation workflow that produces minimal circuit representations for a given system configuration drives our methodology and allows us to analyze any gate set effectively. In this work, we focus on native entangling gates (CNOT, ECR, CZ, ZZ, XX, Sycamore, √iSWAP), proposed gates (B Gate, 4 √CNOT, - 8 √CNOT), as well as parameterized gates (FSim, XY). By providing a method to evaluate the suitability of algorithms for hardware platforms, this work emphasizes the importance of hardware-software codesign for quantum computing.

关键词： Quantum system Quantum computing Computational modeling Logic gates Parallel processing Benchmark testing hardware Circuit synthesis Topology Integrated circuit modeling

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