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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 852 条记录，以下是61-70 订阅

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Special Session Paper: Exploiting Quality-Energy Tradeoffs with Arbitrary Quantization

Special Session Paper: Exploiting Quality-Energy Tradeoffs w...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Moreau, Thierry Augusto, Felipe Howe, Patrick Alaghi, Armin Ceze, Luis Univ Washington Seattle WA 98195 USA Univ Estadual Campinas Campinas SP Brazil

ISBN: (纸本)9781450351850

Approximate computing aims to expose and exploit quality vs. efficiency tradeoffs to enable ever-more demanding applications on energy-constrained devices such as smartphones, or IoT devices. This paper makes the case for arbitrary quantization as a compelling approximation technique that exposes quality vs. energy tradeoffs and provides practical error guarantees. We present QAPPA (Quality Autotuner for Precision Programmable Accelerators), an autotuning framework for C/C++ programs that automatically minimizes the precision of each arithmetic and memory operation to meet user defined application level quality guarantees. QAPPA integrates energy models of precision scaling mechanisms to produce bandwidth and energy savings estimates for precision scalable accelerator designs. We show that QAPPA can exploit precision scaling mechanisms to meet arbitrary user-provided quality targets on the PERFECT benchmark suite to achieve significant energy savings and memory bandwidth reduction.

关键词： Quantization (signal) Bandwidth Benchmark testing hardware Signal to noise ratio Adders Kernel

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Promises and challenges of mobile embedded system: An industry perspective 06

Promises and challenges of mobile embedded system: An indust...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Woo, Nam-Sung Samsung Electronics

ISBN: (纸本)1595933700

Recent trends of IT industry include Mobile/Portable Solution, Integration and Faster Time-to-Market. These trends impose many interesting challenges to Embedded system development both in hardware and software. In this talk, we will first identify some of the challenges. Then, we will present both the current status and plans of Samsung Electronics (in particular, Samsung Semiconductor) to address and overcome the challenges. © Copyright 2006 ACM.

关键词： Information technology

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HSAemu - A Full system Emulator for HSA Platforms 14

HSAemu - A Full System Emulator for HSA Platforms

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Ding, Jiun-Hung Hsu, Wei-Chung Jeng, Bai-Cheng Hung, Shih-Hao Chung, Yeh-Ching Natl Tsing Hua Univ Hsinchu 30013 Taiwan Natl Taiwan Univ Taipei 10617 Taiwan

ISBN: (纸本)9781450330510

Heterogeneous system Architecture (HSA) is an open industry standard designed to support a large variety of data-parallel and task-parallel programming models. Currently, most of HSA hardware and software components are still in development. It is helpful to provide various heterogeneous simulation environments for HSA developers in developing HSA software stacks. This paper presents the design of HSAemu, a full system emulator for the HSA platform, and illustrates how those HSA features are implemented in the simulator. HSAemu provides an infrastructure of heterogeneous simulation environments by supporting required HSA features, including hUMA, hQ and HSAIL. Based on the infrastructure, HSAemu provide two simulation models, FastSim and DeepSim, for high-speed functional emulation and slow cycle-accurate simulation, respectively. In our preliminary experiments, HSAemu helps test a complete HSA software stack and profile system performance. Our case studies show that HSAemu is very useful as a hardware/software co-design tool for heterogeneous systems.

关键词： HSA GPU simulation parallel simulation

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On-Chip Self-Awareness Using Cyberphysical-systems-On-Chip (CPSoC) 14

On-Chip Self-Awareness Using Cyberphysical-Systems-On-Chip (...

引用

international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Sarma, S. Dutt, N. Gupta, P. Nicolau, A. Venkatasubramanian, N. Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90024 USA

ISBN: (纸本)9781450330510

We presented CPSoC, a self-aware sensor-actuator-rich MPSoC platform that deploys the computation-communication-control codesign of CPS together with cross-layer adaptations to achieve multiple design objectives. The CPSoC paradigm enables on-chip self-awareness (selective or opportunistic) adaptation using the concepts of cross-layer physical and virtual sensing and actuations. In [3] we illustrate CPSoC's potential for self-awareness and cross-layer adaptations using several examples and have developed an FPGA prototype to emulate a typical CPSoC.

关键词： actuators field programmable gate arrays sensors system-on-chip CPSoC paradigm FPGA prototype control-communication-computing system codesign cyberphysical-system-on-chip on-chip cross-layer actuation on-chip cross-layer sensing on-chip self-awareness on-chip sensing physical environment sensor-actuator rich many-core computing platforms Aging Computer architecture Delays Predictive models Quality of service Sensors system-on-chip system-on-chip Field programmable gate arrays Sensors Computer Architecture Quality of service physical environment Prediction models self-awareness actuators Aging Awareness delay

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hardware synthesis from a Recursive Functional Language

Hardware Synthesis from a Recursive Functional Language

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Zhai, Kuangya Townsend, Richard Lairmore, Lianne Kim, Martha A. Edwards, Stephen A. Columbia Univ New York NY 10027 USA

ISBN: (纸本)9781467383219

An Abstraction in hardware description languages stalled at the register-transfer level decades ago, yet few alternatives have had much success, in part because they provide only modest gains in expressivity. We propose to make a much larger jump: a compiler that synthesizes hardware from behavioral functional specifications. Our compiler translates general Haskell programs into a restricted intermediate representation before applying a series of semantics-preserving transformations, concluding with a simple syntax-directed translation to systemVerilog. Here, we present the overall framework for this compiler, focusing on the intermediate representations involved and our method for translating general recursive functions into equivalent hardware. We conclude with experimental results that depict the performance and resource usage of the circuitry generated with our compiler.

关键词： Functional hardware Recursion High-Level synthesis

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A New hardware Trojan Design: Distinguishing Between Trigger Inputs and Functional Inputs Is Difficult: Work-in-Progress

A New Hardware Trojan Design: Distinguishing Between Trigger...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Ge, Minghui Zhang, Ying Li, Sen Yao, Jiaqi Mao, Zhiming Chen, Xin Nanjing Univ Aeronaut & Astronaut NUAA Dept Elect & Informat Engn EIE Nanjing Peoples R China

ISBN: (纸本)9781728191980

In this paper, we propose a new hardware Trojan Design. This design makes all HT trigger inputs have the same impact as functional inputs on output signals. It is difficult to distinguish between trigger inputs and functional inputs. Simultaneously, trigger inputs will not be identified as redundant inputs. This approach can defeat the existing detection methods which identify weakly affecting and red Cant trigger inputs across multiple sequential levels. The proposed HT has stealthiness and general applicability.

关键词： hardware trojan trigger inputs functional inputs

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Optimal Functional-Unit Assignment and Buffer Placement for Probabilistic Pipelines 16

Optimal Functional-Unit Assignment and Buffer Placement for ...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Jiang, Weiwen Sha, Edwin H. -M. Zhuge, Qingfeng Chen, Xianzhang Chongqing Univ Coll Comp Sci Chongqing Peoples R China

ISBN: (纸本)9781450344838

Applications, such as streaming applications, modeled by task graphs can be efficiently executed in a pipelined fashion. In synthesizing application-specific heterogeneous pipelined systems, where to place buffers (called buffer placement) and what type of functional units to execute each task (called functional assignment) are two critical problems. In reality, the execution time of each task may not be fixed, which makes the above two problems much more challenging. In this paper, we model the execution time of each task on different types of functional units as a random variable. Our objective is to obtain the optimal functional assignment and buffer placement, such that the resultant pipeline can satisfy the timing requirement with the minimum cost under the guaranteed confidence probability. This paper presents efficient algorithms to achieve the objective. Experiments show that other techniques cannot find any feasible solutions in many cases while ours can. Even for the cases where they can find feasible solutions, our algorithms achieve the minimum cost which gives a significant reduction on the total cost, compared with existing techniques.

关键词： High-level synthesis application-specific system optimal algorithms probabilistic scenario

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Pareto-optimization-based run-time task scheduling for embedded systems 03

Pareto-optimization-based run-time task scheduling for embed...

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Yang, P Catthoor, F IMEC B-3001 Louvain Belgium

ISBN: (纸本)1581137427

Pareto-set-based optimization can be found in several different areas of embedded system design. One example is task scheduling, where different task mapping and ordering choices for a target platform will lead to different performance/cost tradeoffs. To explore this design space at run-time, a fast and effective heuristic is needed. We have modeled the problem as the well known Multiple Choice Knapsack Problem(MCKP) and have developed a fast greedy heuristic for the run-time task scheduling. To show the effectiveness of our algorithm, examples from randomly generated task graphs and realistic applications are studied. Compared to the optimal dynamic programming solver, the heuristic is more than ten times faster while the result is less than 5% away from the optimum. Moreover, due to its iterative feature, the algorithm is well suitable to be used as an on-line algorithm.

关键词： Pareto optimization scheduling embedded system lowpower

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hardware/software Co-design for A Wireless Sensor Network Platform 14

Hardware/Software Co-design for A Wireless Sensor Network Pl...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Hsieh, Chih-Ming Samie, Farzad Srouji, M. Sammer Wang, Manyi Wang, Zhonglei Henkel, Joerg KIT CES Karlsruhe Germany

ISBN: (纸本)9781450330510

Wireless sensor networks have become shared resources providing sensing services to monitor ambient environment. The tasks performed by the sensor nodes and the network structure are becoming more and more complex so that they cannot be handled efficiently by traditional sensor nodes any more. The traditional sensor node architecture, which has software implementation running on a fixed hardware design, is no longer fit to the changing requirements when new applications with complex computation are added to this shared infrastructure due to several reasons. First, the operation behavior changes because of the application requirements and the environmental conditions which makes a fixed architecture not efficient all the time. Second, to collaborate with other already deployed sensor networks and to maintain an efficient network structure, the sensor nodes require flexible communication capabilities. Furthermore, the information required to determine an efficient hardware/software co-design under the system constraints cannot be known a priori. Therefore a platform which can adapt to run-time situations will play an important role in wireless sensor networks. In this paper, we present a hardware/software co-design framework for a wireless sensor platform, which can adaptively change its hardware/software configuration to accelerate complex operations and provides a flexible communication mechanism to deal with complex network structures. We perform real-world measurements on our prototype to analyze its capabilities. In addition, our case studies with prototype implementation and network simulations show the energy savings of the sensor network application by using the proposed design with run-time adaptivity.

关键词： reconfiguration sensor networks hardware accelerator FPGA low power multi-radio

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Reliable software for unreliable hardware: Embedded code generation aiming at reliability 11

Reliable software for unreliable hardware: Embedded code gen...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Rehman, Semeen Shafique, Muhammad Kriebel, Florian Henkel, Jörg Karlsruhe Germany

ISBN: (纸本)9781450307154

A compilation technique for reliability-aware software transformations is presented. An instruction-level reliability estimation technique quantifies the effects of hardware-level faults at the instruction-level while considering spatial and temporal vulnerabilities. It bridges the gap between hardware - where faults occur according to our fault model - and software (the abstraction level where we aim to increase reliability). For a given tolerable performance overhead, an optimization algorithm compiles an application software with respect to a tradeoff between performance and reliability. Compared to performance-optimized compilation, our method incurs 60%-80% lower application failures, averaged over various fault injection scenarios and fault rates. Copyright 2011 ACM.

关键词： Embedded systems

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