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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 853 条记录，以下是701-710 订阅

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Design space minimization with timing and code size optimization for embedded DSP

Design space minimization with timing and code size optimiza...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Qingfeng Zhuge Zili Shao Bin Xiao W.H.-M. Sha Department of Computer Science University of Texas at Dallas Richardson Texas Department of Computer Science University of Texas at Dallas Richardson Texas USA

One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integrated Framework for Design Optimization and Space Minimization (IDOM) towards finding the minimum configuration satisfying timing and code size constraints. We show an effective way to reduce the design space to be explored through the study of the fundamental properties and relations among multiple design parameters, such as retiming value, unfolding factor, timing, and code size. Theories are presented to produce a small set of feasible design choices with provable quality. IDOM algorithm is proposed to generate high-quality design by integrating performance and code size optimization techniques. The experimental results on a set of DSP benchmarks show the efficiency and effectiveness of the IDOM algorithm. It constantly generates the minimal configuration for all the benchmarks. The cost of design space exploration using IDOM is only 3% of that using the standard method.

关键词： Timing Design optimization Digital signal processing Space exploration High level synthesis Algorithm design and analysis Costs

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Designing application specific circuits with concurrent C# programs

Designing application specific circuits with concurrent C# p...

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： David Greaves Satnam Singh Computer Laboratory University of Cambridge Cambridge UK Microsoft Research Cambridge Cambridge UK

This paper presents an investigation into the possibility of using a regular concurrent programming language for modeling and implementing digital circuits. Some of the reasons for using an existing language include the ability to use existing compilers and analysis tools for circuit design and verification. Another important reason is the ever increasing need to model complete systems that comprise interacting software and hardware in a single framework which facilitates easier migration of sub-components between hardware and software implementations compared to multi-model approaches. To this end we present the design of the Kiwi system which models digital circuits with concurrent programs using a standard library in C# for multi-threaded programming. Kiwi models can be executed using a regular C# compiler. Also, the compiled bytecode can be automatically converted into circuits using our Kiwi hardware synthesis system.

关键词： hardware Integrated circuit modeling Message systems Biological system modeling Concurrent computing software Monitoring

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Session details: system modeling 03

Session details: System modeling

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Proceedings of the 1st IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Luciano Lavagno Radu Marculescu Politecnico di Torino Carnegie Mellon University Pittsburgh PA

No abstract available.

ISBN: (纸本)9781581137422

No abstract available.

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Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress

Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks:...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Zhiyuan He Wei Jiang Jinyu Zhan Xupeng Wang Xiangyu Wen School of Information & Software Engineering University of Electronic Science & Technology of China China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promising result, which however suffers from a high computation cost. In this paper, we design a new heatmap-aware method to defend adversarial attacks, leading to a significant decrease in the time cost. To be specific, we compute the classification importance from each part of the input to obtain the heatmap of the data, and the key areas of classification are extracted according to the heatmap. A series of transformations are applied to the key areas of the classification, which reduces the amount of data to be processed and thus reduces the time cost. A set of preliminary experiments are conducted to testify the effectiveness of the proposed approach.

关键词： Heating systems Resists Data mining Task analysis

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hardware Estimation and synthesis for a codesign system

Hardware Estimation and Synthesis for a Codesign System

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international conference on Signal Processing, Communication and Networking (ICSCN)

作者： M. Sangeetha J. RajaPaul Perinbam Revathy College of Engineering Department of Electronics and Communication Engineering Anna University Guindy India Department of Electronics and Communication Engineering S. A. Engineering College Chennai India

A software model of hardware estimator is developed. The behavioral description is transformed into an intermediate format called control flow graph (CFG). The graph is partitioned into hardware and software. The unoptimized hardware in intermediate graph is estimated by transforming the graph into matrix format. The partitioned hardware of control flow graph is translated as behavioral network graph. The high level synthesis and logic synthesis are performed using the BNG with simple logical transformation. The final RTL obtained from the conventional synthesis method and BNG method for resource and timing constraint were presented. The cost estimation for the various control construction is being tabulated

关键词： hardware High level synthesis Logic Network synthesis Synthesizers Resource management Flow graphs Timing Delay Costs

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Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Progress

Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Pro...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Zicheng Gong Wei Jiang Jinyu Zhan Ziwei Song School of Information & Software Engineering University of Electronic Science & Technology of China China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

With increasing applications of Deep Neural Networks (DNNs) to edge computing systems, security issues have received more attentions. Particularly, model stealing attack is one of the biggest challenge to the privacy of models. To defend against model stealing attack, we propose a novel protection architecture with fuzzy models. Each fuzzy model is designed to generate wrong predictions corresponding to a particular category. In addition' we design a special voting strategy to eliminate the systemic errors, which can destroy the dark knowledge in predictions at the same time. Preliminary experiments show that our method substantially decreases the clone model's accuracy (up to 20%) without loss of inference accuracy for benign users.

关键词： Privacy Computational modeling Neural networks Computer architecture Predictive models Security Edge computing

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Session details: system level power modeling and optimization 08

Session details: System level power modeling and optimizatio...

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Proceedings of the 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Ann Gordon-Ross Roman Lysecky University of Florida USA University of Arizona

No abstract available.

ISBN: (纸本)9781605584706

No abstract available.

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Demand paging for OneNANDTM Flash eXecute-in-place

Demand paging for OneNANDTM Flash eXecute-in-place

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Yongseok Choi Eui-Young Chung Naehyuck Chang Sung Woo Chung Chanik Park Yongsoo Joo Seoul National University Korea Yonsei University Korea Samsung Electronics Korea Korea University Korea

NAND flash memory can provide cost-effective secondary storage in mobile embedded systems, but its lack of a random access capability means that code shadowing is generally required, taking up extra RAM space. Demand paging with NAND flash memory has recently been proposed as an alternative which requires less RAM. This scheme is even more attractive for OneNAND flash, which consists of a NAND flash array with SRAM buffers, and supports eXecute-ln-Place (XIP), which allows limited random access to data on the SRAM buffers. We introduce a novel demand paging method for OneNAND flash memory with XIP feature. The proposed on-line demand paging method with XIP adopts finite size sliding window to capture the paging history and thus predict future page demands. We particularly focus on non-critical code accesses which can disturb real-time code. Experimental results show that our method outperforms conventional LRU-based demand paging by 57% in terms of execution time and by 63% in terms of energy consumption. It even beats the optimal solution obtained from MIN, which is a conventional off-line demand paging technique by 30% and 40% respectively.

关键词： Random access memory Embedded system Read-write memory Energy consumption Memory management Algorithm design and analysis Permission system-on-a-chip Decoding User interfaces

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Session details: system level design: throughput, dependability, coherence, and yield 08

Session details: System level design: throughput, dependabil...

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Proceedings of the 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Prabhat Mishra Frank Vahid University of Florida USA University of California at Riverside

No abstract available.

ISBN: (纸本)9781605584706

No abstract available.

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The Integration and Testing Procedures for the AcubeSAT Nanosatellite's software 20

The Integration and Testing Procedures for the AcubeSAT Nano...

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20th international conference on synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024

作者： Keremidis, Antonios Tzelepis, Stylianos Hatzopoulos, Alkis National Technical University of Athens Greece SpaceDot Greece Aristotle University of Thessaloniki Greece AUTh Electronics Lab Dept. of Electrical and Computer Eng Greece

ISBN: (纸本)9798350351927

The AcubeSAT space mission, a collaborative effort within the Fly Your Satellite! 3 program of the European Space Agency (ESA) Education Office and SpaceDot, features unique payload requirements aimed at exploring the effects of radiation and microgravity on eukaryotic cells in Low Earth Orbit (LEO). To address these specialized needs, custom Printed Circuit Board (PCB)s were developed, bypassing off-the-shelf solutions for greater efficiency of the mission and cost-effectiveness. However, this decision introduced a notable challenge: the development of complex system software to ensure the successful execution of all mission phases and the secure transmission of scientific data back to Earth. In this paper, we report on the status of the development and validation processes for the satellite software in its current state, on custom hardware to ensure mission success. © 2024 IEEE.

关键词： Integration testing

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