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international conference on hardware/software codesign and system synthesis (CODES)

作者： S. Cotterell F. Vahid Walid Najjar H. Hsieh Department of Computer Science and Engineering Center for Embedded Computer Systems at UC lrvine University of California Riverside USA

ISBN: (纸本)9781581137422

We describe our first efforts to develop a set of off-the-shelf hardware components that ordinary people could connect to build a simple but useful class of embedded systems. The class of systems, which we call monitor/control systems, is composed primarily of sensors - light, motion, sound, contact, and other types - and output devices - light-emitting diodes, beeping speakers, or even electric relays that control electric appliances like lamps. For example, one monitor/control system would detect if a house's garage door was open at night, and would blink a LED inside the house to alert the homeowner this normally undesirable situation. Today, configuring even the most basic monitor/control system requires knowledge of electronics and programming. We seek to create a set of building blocks, which we call eBlocks, which would enable someone with no knowledge of electronics or programming to be able to build simple but useful monitor/control systems. We are creating eBlocks largely by incorporating intelligence into previously dumb sensors and output devices, and by developing a set of standards and methods that enable eBlocks to work together seamlessly when connected. eBlocks have only recently become possible due to the extremely low cost, low power, and small size of embedded microprocessors. We describe our first results of creating a basic class of eBlocks, Boolean eBlocks, that from a user's perspective transmit or receive only "yes" or "no" signals. We discuss the internal eBlock design, eBlock system design issues and decisions, and several eBlock-based systems designed by ourselves and by undergraduate students.

关键词： Embedded system Control systems Monitoring Motion control Lighting control Light emitting diodes Intelligent sensors hardware Sensor systems Acoustic sensors

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system-level design tools: who needs them, who has them, and how much should they cost?

System-level design tools: who needs them, who has them, and...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： R. Bergamaschi G. Martin G. Smith P. Paulin R. Fordham P. Hardee B. Bailey CoWare Inc. USA Design Verification and Test Division Mentor Graphics USA IBM Thomas J. Watson Research Center Yorktown Heights NY USA Cadence Berkeley Laboratories Berkeley CA USA Gartner Dataquest Inc. USA STMicroelectronics Inc. Canada Motorola Global Software Group USA

CAD vendors are always faced with the question of what tools to develop and how much can they charge for them. Designers on the other hand have real problems to solve and before investing in tools they have to assess how much a given tool will actually save them. CAD vendors and designers have to estimate the savings in design time and cost that a tool may provide and compare that with the existing way of doing things, to determine if the investment in tool creation is justified. For example, if a misguided architectural decision causes weeks of delay because of missing performance targets, then a tool for early architectural analysis may be very valuable. system-level design poses exactly these types of questions because it involves optimizations and analyses across many domains, from software, to architecture, to cycle-time, and is done very early in the design cycle where it has a profound impact. This panel will bring together industry experts to review the current and future industry needs for system-level design technologies as well as discuss how much saving in design time and cost such tools can hope to achieve and whether the designers believe the price is right for the return they can get.

关键词： system-level design Costs Design automation Superluminescent diodes Companies Performance analysis Mathematical model Investments Design engineering software performance

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RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress

RePAiR: A Strategy for Reducing Peak Temperature while Maxim...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Shounak Chakraborty Sangeet Saha Magnus Sjalander Klaus McDonald-Maier Norwegian University of Science and Technology (NTNU) Trondheim Norway Embedded and Intelligent Systems Laboratory University of Essex Colchetser UK

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

Improving accuracy in approximate real-time computing without violating thermal-energy constraints of the underlying hardware is a challenging problem. The execution of approximate real-time tasks can individually be bifurcated into two components: (i) execution of the mandatory part of the task to obtain a result of acceptable quality, followed by (ii) partial/complete execution of the optional part, which refines the initially obtained result, to increase the accuracy without violating the temporal-deadline. This paper introduces RePAiR, a novel task-allocation strategy for approximate real-time applications, combined with fine-grained DVFS and on-line task migration of the cores and power-gating of the last level cache, to reduce chip-temperature while respecting both deadline and thermal constraints. Furthermore, gained thermal benefits can be traded against system-level accuracy by extending the execution-time of the optional part.

关键词： Maintenance engineering Real-time systems hardware Task analysis

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Accelerating Queries of MongoDB by an FPGA-based Storage Engine: Work-in-Progress

Accelerating Queries of MongoDB by an FPGA-based Storage Eng...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jinyu Zhan Junting Wu Wei Jiang Ying Li Jianping Zhu School of Information & Software Engineering University of Electronic Science & Technology of China China Tencent Technology Shenzhen Company Ltd China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

In this paper, we propose a storage engine for MongoDB to accelerate the queries and reduce the memory usage. An FPGA-based query accelerator is deployed to speed up the queries while hot data is migrated from memory to SSD to reduce memory occupancy by our storage engine. Moreover, multiple query tasks of MongoDB are performed in parallel and query conditions are parameterized to support diversified queries. Based on TPC- H benchmark and Tencent data set, experimental results demonstrate that our storage engine can achieve higher query efficiency (saving up to 63.5 % time overhead) and lower memory occupancy (reducing up to 73.4 % memory usage) compared with traditional MongoDB.

关键词： Memory management Benchmark testing Acceleration Task analysis Engines Field programmable gate arrays

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Energy minimization for real-time systems with (m, k)-guarantee

Energy minimization for real-time systems with (<i>m</i>, <i...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Niu, Linwei Quan, Gang Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

Energy consumption and quality of service (QoS) are two primary concerns in the development of today's pervasive computing systems. While most of the current research in energy-aware real-time scheduling has been focused on hard real-time systems, a large number of practical applications and systems exhibit more soft real-time nature. In this paper, we study the problem of minimizing energy for soft real-time systems while providing a QoS guarantee. The QoS requirements are deterministically quantified with the (m, k)-constraints, which require that at least m out of any k consecutive jobs of a task meet their deadlines. In this paper, we propose a hybrid approach to achieve the dual goals of QoS guarantee and energy minimization. We first present the necessary and sufficient schedulability conditions for the static mandatory/optional workload partitioning. Then, we propose to dynamically vary the statically defined mandatory/optional partitions to accommodate dynamic run-time variations while minimizing the energy consumption. The experimental results demonstrate that our proposed techniques outperform previous work significantly in terms of both the energy savings and achieved QoS.

关键词： dynamic volage scaling (DVS) earliest deadline first (EDF) embedded system quality of service (QoS) real-time scheduling

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Complexity management in system-level design

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JOURNAL OF VLSI SIGNAL PROCESSING systemS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 1996年第2期14卷 157-169页

作者： Kalavade, A Lee, EA Dept. of EECS University of California at Berkeley Berkeley CA United States

The system-level design problem spans a large design space. Typically, the designer needs to explore possible target architectures, experiment with different tools, and work with a range of constraints and optimization criteria. This design process is quite complex and involves considerable bookkeeping and management, in addition to sophisticated design tools. We believe that managing the design process is an important (although often neglected) part of system-level design. The contribution of this paper is in two parts. First, we present a framework for systematically managing the design process. Secondly, we illustrate how this framework can be used to manage a system-level design environment that consists of a suite of sophisticated hardware and software design tools. We begin by identifying some of the desirable features of system-level design methodology management. A candidate framework that manifests these features is presented. Complex design flows with iterative and conditional behavior can be specified within the framework. The framework also supports automated scheduling of tools in a well-defined design flow. It has been implemented as the DMM domain in Ptolemy. In the second part of the paper, we describe a case study that we have developed within this framework. The case study, called the Design Assistant, is a complete hardware-software codesign environment. It encapsulates various codesign tools for specification, partitioning, and synthesis;their interplay can be managed efficiently by the design methodology management framework.

关键词： Microprocessor chips

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Architecture and synthesis for multi-cycle on-chip communication 03

Architecture and synthesis for multi-cycle on-chip communica...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： J. Cong Yiping Fan Guoling Han Xun Yang Zhiru Zhang Computer Science Department University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781581137422

There are two important infection points in the development of deep submicron (DSM) process technologies. The first point is when the average interconnect delay exceeds the gate delay, which happened during mid 1990s and led to the so-called timing closure problem. The second point is when single-cycle full chip synchronization is no longer possible, which is about to happen soon. It can be shown that, even with the aggressive interconnect optimization techniques (e.g., buffer insertion and wire-sizing), 5 clock cycles are still needed to go from corner-to-corner for the die of 28.3 mm /spl times/ 28.3 mm in the 0.07 /spl mu/m technology generation, assuming a 5.63 GHz clock by 2006 predicted in ITRS'01 (2001). This clearly suggests that multi-cycle on-chip communication is a necessity in multi-gigahertz synchronous designs. However, it is not supported in the current design tools and methodologies, as most of these implicitly assume that full chip synchronization in a single clock cycle is feasible. Our contributions are as follows: (i) we propose a regular distributed register (RDR) microarchitecture which offers high regularity and direct support of multi-cycle communication; (ii) we develop a set of novel architectural synthesis algorithms to efficiently synthesize behavior-level designs onto the RDR architecture.

关键词： Clocks Registers Design methodology Computer architecture Delay Distributed computing Integrated circuit interconnections Synchronization Signal design Communication system control

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A High-Speed, Area-Optimized, ROM-Less (Co)Sine Wave synthesis Accelerator 16

A High-Speed, Area-Optimized, ROM-Less (Co)Sine Wave Synthes...

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16th international Symposium on Electronics and Telecommunications, ISETC 2024

作者： Stoica, Florentina-Giulia Calinescu, Alex Enachescu, Marius Electronic Devices Circuits and Architectures University Politehnica of Bucharest Faculty of Electronics Telecommunications and Information Technology Bucharest Romania

ISBN: (纸本)9798350390865

Sine and cosine wave synthesis is utilized for generating sinusoidal-alike values in the digital domain. While this task is handled through software, dedicated hardware like Direct Digital synthesis (DDS) is also available. However, both methods rely on memory resources, such as look-up tables and Read-Only Memories (ROMs), which face latency limitations related to additional memory access times on top of additional Si area. With the advent of real-time arithmetic for sine wave approximation, this paper presents an all-in-one digital module that employs iterative multiply-accumulate (MAC) operations for sine and cosine synthesis, ready to be integrated in systems-on-Chip (SoCs), Field Programmable Gate Arrays (FPGAs), or even standalone ASICs. Compared to ROM-less solutions like Taylor approximation, the proposed architecture achieves 80.80% lower resource utilization, 80.39% reduced propagation delay, and 36.66% higher accuracy in sine and cosine wave approximation, both operating as 32-bit systems with one sample per clock cycle. © 2024 IEEE.

关键词： system-on-chip

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Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip

Bus architecture synthesis for hardware-software co-design o...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： N. Thepayasuwan Vaishali Damle A. Doboli Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

system level design always has a disadvantage of not possessing detailed knowledge of the communication subsystem. This is a crucial issue for system-on-chip design, where uncertainty in communication by very deep submicron effects cannot be neglected. We present a bus architecture (BA) synthesis algorithm for designing the communication subsystem of an SoC. The algorithm is part of a hardware-software codesign methodology for resource constrained embedded applications. BA synthesis includes finding the bus topology, and routing the individual buses so that various constraints, like bus length, topology complexity, potential for communication conflicts over time, are addressed. We present BA synthesis results for a network processor, and a JPEG SoC.

关键词： system-on-a-chip Routing Application software Computer architecture system-level design Algorithm design and analysis Network synthesis Network topology Analog-digital conversion Delay

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Compile-time decided instruction cache locking using worst-case execution paths

Compile-time decided instruction cache locking using worst-c...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Heiko Falk Sascha Plazar Henrik Theiling Computer Science 12 University of Dortmund Dortmund Germany AbsInt Angewandte Informatik GmbH Saarbrucken Germany

Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability is highly undesired for real-time systems. The Worst-Case Execution Time (WCET) of a software running on an embedded processor is one of the most important metrics during real-time system design. The WCET depends to a large extent on the total amount of time spent for memory accesses. In the presence of caches, WCET analysis must always assume a memory access to be a cache miss if it can not be guaranteed that it is a hit. Hence, WCETs for cached systems are imprecise due to the overestimation caused by the caches. Modern caches can be controlled by software. The software can load parts of its code or of its data into the cache and lock the cache afterwards. Cache locking prevents the cache's contents from being flushed by deactivating the replacement. A locked cache is highly predictable and leads to very precise WCET estimates, because the uncertainty caused by the replacement strategy is eliminated completely. This paper presents techniques exploring the lockdown of instruction caches at compile-time to minimize WCETs. In contrast to the current state of the art in the area of cache locking, our techniques explicitly take the worst-case execution path into account during each step of the optimization procedure. This way, we can make sure that always those parts of the code are locked in the I-cache that lead to the highest WCET reduction. The results demonstrate that WCET reductions from 54% up to 73% can be achieved with an acceptable amount of CPU seconds required for the optimization and WCET analyses themselves.

关键词： Benchmark testing Optimization Algorithm design and analysis Context software Transform coding Real time systems

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