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Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip

Bus architecture synthesis for hardware-software co-design o...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： N. Thepayasuwan Vaishali Damle A. Doboli Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

system level design always has a disadvantage of not possessing detailed knowledge of the communication subsystem. This is a crucial issue for system-on-chip design, where uncertainty in communication by very deep submicron effects cannot be neglected. We present a bus architecture (BA) synthesis algorithm for designing the communication subsystem of an SoC. The algorithm is part of a hardware-software codesign methodology for resource constrained embedded applications. BA synthesis includes finding the bus topology, and routing the individual buses so that various constraints, like bus length, topology complexity, potential for communication conflicts over time, are addressed. We present BA synthesis results for a network processor, and a JPEG SoC.

关键词： system-on-a-chip Routing Application software Computer architecture system-level design Algorithm design and analysis Network synthesis Network topology Analog-digital conversion Delay

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MARS: mm Wave-based Assistive Rehabilitation system for Smart Healthcare

MARS: mm Wave-based Assistive Rehabilitation System for Smar...

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international conference on hardware/software codesign and system synthesis (CODES plus ISSS)

作者： An, Sizhe Ogras, Umit Y. Univ Wisconsin Dept Elect & Comp Engn Madison WI 53706 USA

Rehabilitation is a crucial process for patients suffering from motor disorders. The current practice is performing rehabilitation exercises under clinical expert supervision. New approaches are needed to allow patients to perform prescribed exercises at their homes and alleviate commuting requirements, expert shortages, and healthcare costs. Human joint estimation is a substantial component of these programs since it offers valuable visualization and feedback based on body movements. Camera-based systems have been popular for capturing joint motion. However, they have high-cost, raise serious privacy concerns, and require strict lighting and placement settings. We propose a millimeter-wave (mmWave)-based assistive rehabilitation system (MARS) for motor disorders to address these challenges. MARS provides a low-cost solution with a competitive object localization and detection accuracy. It first maps the 5D time-series point cloud from mmWave to a lower dimension. Then, it uses a convolution neural network (CNN) to estimate the accurate location of human joints. MARS can reconstruct 19 human joints and their skeleton from the point cloud generated by mmWave radar. We evaluate MARS using ten specific rehabilitation movements performed by four human subjects involving all body parts and obtain an average mean absolute error of 5.87 cm for all joint positions. To the best of our knowledge, this is the first rehabilitation movements dataset using mmWave point cloud. MARS is evaluated on the Nvidia Jetson Xavier-NX board. Model inference takes only 64 mu s and consumes 442 mu J energy. These results demonstrate the practicality of MARS on low-power edge devices.

关键词： Human pose estimation point cloud millimeter wave smart healthcare

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system-level reliability modeling for MPSoCs

System-level reliability modeling for MPSoCs

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作者： Xiang, Yun Chantem, Thidapat Dick, Robert P. Hu, X. Sharon Shang, Li EECS Department University of Michigan Ann Arbor MI 48109 United States CSE Department University of Notre Dame Notre Dame IN 46556 United States ECE Department University of Colorado Boulder CO 80309 United States

ISBN: (纸本)9781605589053

The reliability of multi-processor systems-on-chip (MPSoCs) is affected by several inter-dependent system-level and physical effects. Accurate and fast reliability modeling is a primary challenge in the design and optimization of reliable MPSoCs. This paper presents a reliability modeling framework that integrates device-, component-, and system-level models. This framework contains modules for electromigration, time-dependent dielectric breakdown, stress migration, and variable-amplitude thermal cycling. A new statistical reliability distribution is proposed for accurate characterization of components containing too few devices for an extreme value distribution to be appropriate. A hierarchical system-level survival lattice based Monte Carlo technique is used to estimate the temporal fault distributions of MPSoCs that use arbitrary static and dynamic reliability-enhancing redundancy schemes. Physical process variation, which may have a significant impact on MPSoC reliability, is considered in the model. The proposed modeling technique has 5% average error in mean time to failure and reduces simulation time by nearly 3 orders of magnitude relative to a non-hierarchical Monte Carlo technique. © 2010 ACM.

关键词： Hierarchical systems

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Analytical models for leakage power estimation of memory array structures 04

Analytical models for leakage power estimation of memory arr...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： M. Mamidipaka K. Khouri N. Dutt M. Abadir Center for Embedded Computer Systems University of California Irvine CA USA Global Strategy and Future Tools & Meth. Freescale/Motorola Inc. Austin TX USA

ISBN: (纸本)9781581139372

There is a growing need for accurate power models at the system level. Memory structures such as caches, branch target buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates against the leakage power measured using SPICE simulations on industrial array designs belonging to the e500 processor core. The comparison shows that the models are accurate with an error margin of less than 21.5% and thus can be used in high-level power-performance exploration. Interestingly, in array designs with dual threshold voltage technology, we observed that contrary to the general expectation, the array memory core contributes to just 9% and the address decoder contributes to as much as 62% of the total leakage power.

关键词： Analytical models Power dissipation Power system modeling SPICE Embedded computing Registers Circuit simulation Power measurement Threshold voltage Decoding

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A Platform-based SoC hardware/software Co-Design Environment

A Platform-based SoC Hardware/Software Co-Design Environment

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The 8th international conference on Computer Supported Cooperative Work in Design(第八届计算机支持的协同工作设计国际会议)(CSCWD2004)

作者： Zhihui Xiong Sikun Li Jihua Chen Dawei Wang School of Computer Science National University of Defense TechnologyChangshaP.R.China410073

ISBN: (纸本)0780379411

This paper presents a Platform-based SoChardware/software co-design environment namedHSCDE. It introduces the overall structure of HSCDE,describes the Platform-based SoC system modelingtechnology, ant algorithm based hardware/softwarepartitioning technology and Hierarchical DirectedAcyclic Graph based performance constraintassignment technology. HSCDE supports Platform-based SoC hardware/software co-design *** supports almost all the design phases from SoCsystem modeling to RTL level SoC system. It dividesSoC hardware/software co-design into system modelinglevel (level 1), virtual components level (level 2) andreal components level (level 3), and it performs the 2mappings among the 3 design levels by DesignPlanning (mapping 1) and Virtual-Real synthesis(mapping 2). We have clone SoC system design for MP3player SoC, MEPG2 player SoC and CDMA wirelesscommunication SoC in HSCDE environment. Resultsshow that HSCDE effectively supports Platform-basedSoC hardware/software co-design methodology;itenhanced system reuse of existing SoC design. Statisticsindicate an average of 10％～25％ revisions on platformtemplates for a new SoC design, and we achievedplatform template reuse ratio by 75％～90％.

关键词： hardware-software codesign system-on-chip directed graphs logic design integrated circuit design SoC hardware-software codesign HSCDE SoC system modeling hardware-software partitioning hierarchical directed acyclic graph performance constraint assignment technology RTL level SoC system virtual components level virtual-real synthesis MP3 player SoC MEPG2 player SoC CDMA wireless communication SoC

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How to improve the space utilization of dedup-based PCM storage devices? 15

How to improve the space utilization of dedup-based PCM stor...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chun-Ta Lin Yuan-Hao Chang Tei-Wei Kuo Hung-Sheng Chang Hsiang-Pang Li Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan R.O.C. Institute of Information Science Academia Sinica Taipei Taiwan R.O.C. Research Center for Information Technology Innovation Academia Sinica Taipei Taiwan R.O.C. Macronix International Co. Ltd. Emerging System Lab. Hsinchu Taiwan R.O.C.

ISBN: (纸本)9781467383219

There is a growing demand to introduce more and more intelligence to storage devices in recent years, especially with the rapid increasing of hardware computing power. This paper targets on essential design issues in space utilization for dedup-based non-volatile phase-change memory (PCM). We explore the adoption of data duplication techniques to reduce potential data duplicates over PCM storage devices to provide more storage space than the physical storage space does. Among various data deduplication techniques, variable-sized chunking is considered in less cost-effective PCM-based storage devices because variable-sized chunking has better data deduplication capability than fixed-sized chunking. However, in a typical system architecture, data are written or updated in the fixed management units (e.g., LBAs). Thus, to ultimately improve the space utilization of PCM-based storage device, the technical problem falls on (1) how to map fixed-sized LBAs to variable-sized chunks and (2) how to efficiently manage (i.e., allocated and deallocate) free PCM storage space for variable-sized chunks. In this work, we propose a free space manager, called container-based space manager, to resolve the above two issues by exploiting the fact that (1) a storage system initially has more free space to relax the complexity on space management and (2) the space optimization of a storage system can grow with the time when it contains more and more data. The proposed design is evaluated over popular benchmarks, for which we have very encouraging results.

关键词： Phase change materials Power capacitors Performance evaluation Ash Computer architecture Random access memory Media

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A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control

A buffer-sizing algorithm for networks on chip using TDMA an...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Andrei Ruadulescu Kees Goossens Giovanni De Micheli Srinivasan Murali Martijn Coenen Philips Research Eindhoven The Netherlands CSL Stanford University Stanford USA LSI Switzerland LSI EPFL Switzerland

When designing a system-on-chip (SoC) using a network- on-chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power consumption is due to the buffers in the network interfaces (NIs) needed to decouple computation from communication. Having such a decoupling prevents stalling of IP blocks due to the communication interconnect. The size of these buffers is especially important in real-time systems, as there they should be big enough to obtain predictable performance. To ensure that buffers do not overflow, end- to-end flow-control is needed. One form of end-to-end flow- control used in NoCs is credit-based flow-control. This form places additional requirements on the buffer sizes, because the flow-control delays need to be taken into account. In this work, we present an algorithm to find the minimal decoupling buffer sizes for a NoC using TDMA and credit- based end-to-end flow-control, subject to the performance constraints of the applications running on the SoC. Our experiments show that our method results in a 84% reduction of the total NoC buffer area when compared to the state-of- the art buffer-sizing methods. Moreover, our method has a low run-time complexity, producing results in the order of minutes for our experiments, enabling quick design cycles for large SoC designs. Finally, our method can take into account multiple usecases running on the same SoC.

关键词： Network-on-a-chip Time division multiple access Communication system control system-on-a-chip Energy consumption Silicon Design optimization Network interfaces Computer interfaces Computer networks

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An ESL Methodology for HW/SW Co-Design of Monitorable Embedded systems: the “Design for Monitorability” Project - Work-in-Progress

An ESL Methodology for HW/SW Co-Design of Monitorable Embedd...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Giacomo Valente Tania Di Mascio Luigi Pomante Vincenzo Stoico DISIM/DEWS Università degli Studi dell'Aquila ITALY

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

This paper proposes an Electronic system-Level (ESL) Methodology for HW/SW Co-Design of Monitorable Embedded systems. In particular, this paper aims to define an innovative topic called Design for Monitorability (DfM). DfM exploits ESL HW/SW co-design techniques to satisfy Monitorability Requirements (M_REQs) by considering them since the initial steps of the HW/SW co-design flow as additional ones. DfM has the final goal of suggesting to the designer an On-Chip Monitoring system (OCMS) able to satisfy M _ REQs., to be integrated in the final system (i.e., possibly heterogeneous and/or parallel SoCs) while still respecting the other possible nonfunctional requirements imposed to the system implementation (e.g., execution time, area/resource utilization, energy consumption, etc.). The description of the motivations and the main concepts behind the proposed methodology represent the core of the paper.

关键词： Energy consumption Embedded systems system-on-chip Monitoring system implementation

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Research on Intelligent Relic Interpretation system Based on a Large Language Model 24

Research on Intelligent Relic Interpretation System Based on...

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24th IEEE international conference on software Quality, Reliability and Security Companion, QRS-C 2024

作者： Guo, Jingjing Han, Xi Beijing Union University Beijing Key Laboratory of Information Service Engineering Beijing China College of Robotics Beijing Union University Beijing China

ISBN: (纸本)9798350365658

Nowadays, docents are the main force for inheriting and displaying human cultural heritage. However, the experience of visitors largely depends on their knowledge depth and updates. Large language models (LLMs) have demonstrated promising results across various fields due to their robust linguistic intelligence acquired through extensive data training. Nevertheless, training LLMs remains challenging due to their high hardware requirements. How can we integrate a LLM into a relic interpretation system without the need for extensive training? To this end, a solution is proposed by combining a LLM with a private domain database to create an intelligent relic interpretation system. This system encompasses the following functionalities:(1) Speech recognition and synthesis: Users input speech, and the system utilizes speech recognition technology to convert the speech into text. This text is then processed by the LLM, and the model's responses are synthesized into speech output;(2) Professional knowledge explanation: Leveraging a LLM and a private domain database to achieve more accurate and professional responses, compared to simply fine-tuning LLMs, this allows for the application of LLMs in vertical fields without the need for additional training;(3) Private domain database renewal: Two methods for updating the database are used: extracting relevant data from intranet sources and uploading data by professionals. The performance of the system is evaluated through comparison and ablation experiments. The results demonstrate that the system effectively addresses the limitations of traditional relic interpretation methods and introduces novel perspectives for relic interpretation. © 2024 IEEE.

关键词： Speech recognition

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Soft Errors: The hardware-software Interface 12

Soft Errors: The Hardware-Software Interface

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ACM international conference on hardware/software - codesign and system synthesis

作者： Kyoungwoo Lee Aviral Shrivastava Reiley Jeyapaul Yonsei University Seoul South Korea Arizona State University Phoenix USA

ISBN: (纸本)9781450314268

A recent report from the ITRS identifies soft errors, as one of the most important reliability challenges for the coming decades. Soft errors are transient errors caused by several effects e.g., voltage fluctuations, wire-cross talks, and cosmic particle strikes; and manifest as a temporary switch of the logic value of a transistor. While it is not possible to prove nor disprove that a certain error happened due to soft errors, several fiscal disasters e.g., Sun server crashes in 2000, and HP server crashes in 2005, have been attributed to soft errors. Industry has moved from the position of ignoring soft errors to adding design efforts for protection from them. For instance, in the recently announced nVIDIA's Fermi GPUs, the L1 cache, L2 cache and register files are ECC protected. Although the soft error rate is about once-per year today, it is expected to reach alarming levels of once-per-day in about a decade or two. Researchers are busy finding cost-effective solutions to protect computing devices from soft errors. This tutorial will attempt to cover the entire gamut of soft error protection techniques, but will particularly focus on the soft error mitigation techniques at the hardware/software interface. Much time will be spent on microarchitectural, compiler, and hybrid compiler-microarchitectural techniques for soft error mitigation. This tutorial will be particularly useful for budding researchers who are fascinated by soft errors, and want to explore this as their research direction. For such researchers, this tutorial will be a one-stop-shop to acquire knowledge of and analyze seminal research work in the field of soft error mitigation, at several design layers. For developers who have been working on soft errors at different levels, this will give them a picture of what can be done at other levels, so that they can provide complementary cross-layer protection. Finally, researchers and developers working on other aspects of system design can learn how soft

关键词： Soft error mitigation compiler microarchitectural techniques

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