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system-level reliability modeling for MPSoCs

System-level reliability modeling for MPSoCs

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作者： Xiang, Yun Chantem, Thidapat Dick, Robert P. Hu, X. Sharon Shang, Li EECS Department University of Michigan Ann Arbor MI 48109 United States CSE Department University of Notre Dame Notre Dame IN 46556 United States ECE Department University of Colorado Boulder CO 80309 United States

ISBN: (纸本)9781605589053

The reliability of multi-processor systems-on-chip (MPSoCs) is affected by several inter-dependent system-level and physical effects. Accurate and fast reliability modeling is a primary challenge in the design and optimization of reliable MPSoCs. This paper presents a reliability modeling framework that integrates device-, component-, and system-level models. This framework contains modules for electromigration, time-dependent dielectric breakdown, stress migration, and variable-amplitude thermal cycling. A new statistical reliability distribution is proposed for accurate characterization of components containing too few devices for an extreme value distribution to be appropriate. A hierarchical system-level survival lattice based Monte Carlo technique is used to estimate the temporal fault distributions of MPSoCs that use arbitrary static and dynamic reliability-enhancing redundancy schemes. Physical process variation, which may have a significant impact on MPSoC reliability, is considered in the model. The proposed modeling technique has 5% average error in mean time to failure and reduces simulation time by nearly 3 orders of magnitude relative to a non-hierarchical Monte Carlo technique. © 2010 ACM.

关键词： Hierarchical systems

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A Platform-based SoC hardware/software Co-Design Environment

A Platform-based SoC Hardware/Software Co-Design Environment

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The 8th international conference on Computer Supported Cooperative Work in Design(第八届计算机支持的协同工作设计国际会议)(CSCWD2004)

作者： Zhihui Xiong Sikun Li Jihua Chen Dawei Wang School of Computer Science National University of Defense TechnologyChangshaP.R.China410073

ISBN: (纸本)0780379411

This paper presents a Platform-based SoChardware/software co-design environment namedHSCDE. It introduces the overall structure of HSCDE,describes the Platform-based SoC system modelingtechnology, ant algorithm based hardware/softwarepartitioning technology and Hierarchical DirectedAcyclic Graph based performance constraintassignment technology. HSCDE supports Platform-based SoC hardware/software co-design *** supports almost all the design phases from SoCsystem modeling to RTL level SoC system. It dividesSoC hardware/software co-design into system modelinglevel (level 1), virtual components level (level 2) andreal components level (level 3), and it performs the 2mappings among the 3 design levels by DesignPlanning (mapping 1) and Virtual-Real synthesis(mapping 2). We have clone SoC system design for MP3player SoC, MEPG2 player SoC and CDMA wirelesscommunication SoC in HSCDE environment. Resultsshow that HSCDE effectively supports Platform-basedSoC hardware/software co-design methodology;itenhanced system reuse of existing SoC design. Statisticsindicate an average of 10％～25％ revisions on platformtemplates for a new SoC design, and we achievedplatform template reuse ratio by 75％～90％.

关键词： hardware-software codesign system-on-chip directed graphs logic design integrated circuit design SoC hardware-software codesign HSCDE SoC system modeling hardware-software partitioning hierarchical directed acyclic graph performance constraint assignment technology RTL level SoC system virtual components level virtual-real synthesis MP3 player SoC MEPG2 player SoC CDMA wireless communication SoC

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HW/SW Auto-Coupling for Fast IP Integration in SoC Designs

HW/SW Auto-Coupling for Fast IP Integration in SoC Designs

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international conference on Embedded software and systems

作者： Yin-Tsung Hwang Jun-Yen Chen Jun-Jieh Chiu Department of Electrical Engineering National Chung Hsing University Taichung Taiwan

ISBN: (纸本)9780769532875

IP intergration in SoC nowadays contains two design aspects, i.e. hardware interface and software driver. The hardware interface supports necessary signal mapping, protocol translation and data buffering so that an IP can adapt to various system architectures. The software driver provides IP access controls from the software domain in the presence of operating system. The automation of both design processes in a coupling manner is addressed in this paper. We first outline the methodology of automatic interface synthesis and elaborate on the topics of signal mapping, protocol conversion and interface template architecture. We next present the framework of a baseline driver generator and detail the generation schemes of basic file operations and other functions and driver settings. Both tools are linked to form a HW/SW auto-coupling design suite, which features minimum user knowledge toward the hardware and OS details in usage. Some design examples on the interface synthesis tool and an JPEG codec HW/SW codesign example on the integrated design suite are provided to prove the effectiveness of the proposed system.

关键词： Driver circuits Protocols hardware IP networks Converters Generators Signal mapping

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How to improve the space utilization of dedup-based PCM storage devices? 15

How to improve the space utilization of dedup-based PCM stor...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chun-Ta Lin Yuan-Hao Chang Tei-Wei Kuo Hung-Sheng Chang Hsiang-Pang Li Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan R.O.C. Institute of Information Science Academia Sinica Taipei Taiwan R.O.C. Research Center for Information Technology Innovation Academia Sinica Taipei Taiwan R.O.C. Macronix International Co. Ltd. Emerging System Lab. Hsinchu Taiwan R.O.C.

ISBN: (纸本)9781467383219

There is a growing demand to introduce more and more intelligence to storage devices in recent years, especially with the rapid increasing of hardware computing power. This paper targets on essential design issues in space utilization for dedup-based non-volatile phase-change memory (PCM). We explore the adoption of data duplication techniques to reduce potential data duplicates over PCM storage devices to provide more storage space than the physical storage space does. Among various data deduplication techniques, variable-sized chunking is considered in less cost-effective PCM-based storage devices because variable-sized chunking has better data deduplication capability than fixed-sized chunking. However, in a typical system architecture, data are written or updated in the fixed management units (e.g., LBAs). Thus, to ultimately improve the space utilization of PCM-based storage device, the technical problem falls on (1) how to map fixed-sized LBAs to variable-sized chunks and (2) how to efficiently manage (i.e., allocated and deallocate) free PCM storage space for variable-sized chunks. In this work, we propose a free space manager, called container-based space manager, to resolve the above two issues by exploiting the fact that (1) a storage system initially has more free space to relax the complexity on space management and (2) the space optimization of a storage system can grow with the time when it contains more and more data. The proposed design is evaluated over popular benchmarks, for which we have very encouraging results.

关键词： Phase change materials Power capacitors Performance evaluation Ash Computer architecture Random access memory Media

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Runtime requirements monitoring for state-based hardware: work-in-progress 18

Runtime requirements monitoring for state-based hardware: wo...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Minjun Seo Roman Lysecky University of Arizona

ISBN: (纸本)9781538655627

This paper presents a requirements-driven methodology enabling efficient runtime monitoring of hardware in embedded systems. We present a novel method for extracting hardware verification requirements from state-based hardware models to construct a hierarchical runtime monitoring graph (HRMG) that can be efficiently used at runtime to verify correctness.

关键词： runtime requirements verification formal verification models hardware verification non-intrusive monitoring

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FPGA-based design of a high-performance and modular video processing platform

FPGA-based design of a high-performance and modular video pr...

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IEEE international conference on Electro-Information Technology

作者： Christophe Desmouliers Erdal Oruklu Jafar Saniie Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago IL USA

In this paper, an FPGA-based design and implementation of a high-performance video processing platform (VPP) is presented. A hardware/software codesign system is proposed on Xilinx Virtex II Pro FPGA to realize complex algorithms for real-time image and video processing. This paper presents the framework of the VPP, discusses the architectural building blocks and FPGA synthesis results. Each hardware (custom accelerator blocks) and software (code running on an embedded CPU core) component is described comprehensively, laying the foundation for an adaptable and modular embedded system. As a case study, a real-time motion detection algorithm is implemented, demonstrating the feasibility of the proposed platform. Additional hardware accelerators can be easily plugged-in to the system for desired processing engines. VPP can be a robust, cost-effective solution for a broad range of multimedia applications including broadcasting and streaming video, video on-demand, video encoding/decoding, surveillance, detection and recognition.

关键词： hardware Video on demand Field programmable gate arrays Streaming media software systems software algorithms Real time systems Embedded software Embedded system Motion detection

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Research on Intelligent Relic Interpretation system Based on a Large Language Model 24

Research on Intelligent Relic Interpretation System Based on...

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24th IEEE international conference on software Quality, Reliability and Security Companion, QRS-C 2024

作者： Guo, Jingjing Han, Xi Beijing Union University Beijing Key Laboratory of Information Service Engineering Beijing China College of Robotics Beijing Union University Beijing China

ISBN: (纸本)9798350365658

Nowadays, docents are the main force for inheriting and displaying human cultural heritage. However, the experience of visitors largely depends on their knowledge depth and updates. Large language models (LLMs) have demonstrated promising results across various fields due to their robust linguistic intelligence acquired through extensive data training. Nevertheless, training LLMs remains challenging due to their high hardware requirements. How can we integrate a LLM into a relic interpretation system without the need for extensive training? To this end, a solution is proposed by combining a LLM with a private domain database to create an intelligent relic interpretation system. This system encompasses the following functionalities:(1) Speech recognition and synthesis: Users input speech, and the system utilizes speech recognition technology to convert the speech into text. This text is then processed by the LLM, and the model's responses are synthesized into speech output;(2) Professional knowledge explanation: Leveraging a LLM and a private domain database to achieve more accurate and professional responses, compared to simply fine-tuning LLMs, this allows for the application of LLMs in vertical fields without the need for additional training;(3) Private domain database renewal: Two methods for updating the database are used: extracting relevant data from intranet sources and uploading data by professionals. The performance of the system is evaluated through comparison and ablation experiments. The results demonstrate that the system effectively addresses the limitations of traditional relic interpretation methods and introduces novel perspectives for relic interpretation. © 2024 IEEE.

关键词： Speech recognition

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WiderFrame: An Automatic Customization Framework for Building CNN Accelerators on FPGAs: Work-in-Progress

WiderFrame: An Automatic Customization Framework for Buildin...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Lei Gong Chao Wang Xi Li Xuehai Zhou School of Computer Science and Technology University of Science and Technology of China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

hardware acceleration based on FPGA has been an important means to improve the computational efficiency of CNNs. However, due to the increasing complexity of the modern CNNs and the diversity of neural computing engines, it is challenging to make full use of FPGAs' customizability for efficient and fast accelerator designs. This paper proposes Wider-Frame, an automatic customization framework for building CNN accelerators on FPGA. Towards fully exploiting the customiz-ability of FPGA for specific computing scenarios, WiderFrame integrates a systematical design space exploration methodology considered with different parallel and data reuse manners among various neural computing engines, a parameterized configurable code template with a set of macro instruction mechanism, for automatically generating the underlying hardware units and the control flow. Evaluation results show that WiderFrame can well support more CNN types, and can improve the performance and the energy efficiency up to 1.25 x and 1.68 x compared with state-of-the-art frameworks.

关键词： Design methodology Buildings Energy efficiency Space exploration Field programmable gate arrays Engines hardware acceleration

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hardware implementation of a multi-mode-aware mixed-criticality scheduler: work-in-progress 18

Hardware implementation of a multi-mode-aware mixed-critical...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Sena Hounsinou Aishwarya Vasu Harini Ramaprasad Southern Illinois University University of North Carolina

ISBN: (纸本)9781538655627

To minimize size, weight, power, and cost, the industry aims at consolidating different criticality applications on the same hardware platform. In such a mixed-criticality environment, it is challenging to contain the overhead due to potential mode changes under overload conditions. Traditional scheduler implementation at the software level introduces additional overheads due to timer interrupt processing and context switching. To minimize overall software overhead and to improve timing predictability, in this paper, we propose an implementation of the mixed-criticality scheduler in the hardware that is capable of detecting task-overruns and making mode transitions seamlessly.

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Keynote talk II: Multiform logical time for Me/Mo-codesign

Keynote talk II: Multiform logical time for Me/Mo-codesign

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Robert de Simone Inria Le Chesnay ÃŽle-de-France FR

ISBN: (纸本)9781509027927

There is now a consistent corpus of models and methods for software/hardware codesign (scope of MeMoCoDe). Still, while success is quite established at both ends of the spectrum (High-Level hardware synthesis, and system Engineering), the adoption of such software modeling approach inside mainstream software Engineering communities could easily be improved. This is certainly so because some of the principles of application modeling do not exactly match, or elsewhere do not focus upon the same concerns, as traditional coding style. Putting forth the relevant important concepts for application modeling, while investigating their relevance to traditional engineering experience, is certainly a way to counter confusion. We view the notion of Multiform Logical Time as such a fundamental concept. In a first part of the talk we consider the premises of Multiform Logical Time in Embedded Design (its origin, its relevance at places of design flows); in a second part we introduce a small declarative language to express logical time properties, study its expressiveness and its associated analysis techniques.

关键词： Unified modeling language Embedded systems Semantics Parallel processing Algebra Model checking Collaboration

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