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Coherent Extension, Composition, and Merging Operators in Contract Models for system Design

ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 86-86页

作者： Passerone, Roberto Romeo, Inigo Incer Sangiovanni-Vincentelli, Alberto L. Univ Trento Dipartimento Ingn & Sci Informaz Via Sommar 9 I-38123 Trento Italy Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

Contract models have been proposed to promote and facilitate reuse and distributed development. In this paper, we cast contract models into a coherent formalism used to derive general results about the properties of their operators. We study several extensions of the basic model, including the distinction between weak and strong assumptions and maximality of the specification. We then analyze the disjunction and conjunction operators, and show how they can be broken up into a sequence of simpler operations. This leads to the definition of a new contract viewpoint merging operator, which better captures the design intent in contrast to the more traditional conjunction. The adjoint operation, which we call separation, can be used to repartition the specification into different viewpoints. We show the symmetries of these operations with respect to composition and quotient.

关键词： Interface contract merging conformance separation

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Towards the application of flask security architecture to SoC design: work-in-progress 17

Towards the application of flask security architecture to So...

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Proceedings of the Twelfth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Festus Hategekimana Christophe Bobda University of Arkansas

ISBN: (纸本)9781450351850

In this work, we explore a security reference monitor (RM) design which borrows from the Flask security architecture. Our RM design goal is to achieve complete mediation by checking and verifying the authority and the authenticity of every access to every system object in systems-on-chip (SoCs). Access decisions are administered by a security logic "server" implemented as an extension of the peripheral bus. Initial results show a minimal increase in resource overhead and no significant impact on the performance.

关键词： secure execution trojan hardware sandbox field programmable gate arrays (FPGAs) component authentication process systems-on-chip (SoC)

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The future of system-level design: can we find the right solutions to the right problems at the right time? 03

The future of system-level design: can we find the right sol...

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Proceedings of the 1st IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Reinaldo Bergamaschi Grant Martin Wayne Wolf Rolf Ernst Kees Vissers Jack Kouloheris IBM Research NY Cadence Labs Berkeley CA Princeton University NJ TU Braunschweig Germany UC Berkeley CA

ISBN: (纸本)9781581137422

Over the last 15 years we have seen and helped the evolution of design from behavioral modeling to hardware/software co-design, to today's system-level design. Arguably, many of the research efforts on behavioral synthesis, hardware / software co-design, co-simulation etc. have made their way into successful commercial tools, while others went no further than a conference paper. As we continue and expand system-level research with new approaches opening exciting new research avenues, we have an obligation to look back at our successes and failures. Then looking towards the future, we must answer the question: are we solving the right problems with the right solutions at the right time, or should we go back to the drawing board and think of brand new research *** panel will bring together panelists experienced in various aspects of system-level design who will present different views on what this community has achieved over the last 15 years and draw a roadmap for future research.

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hardware/software partitioning of software binaries: a case study of H.264 decode 05

Hardware/software partitioning of software binaries: a case ...

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Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Greg Stitt Frank Vahid Gordon McGregor Brian Einloth University of California Riverside Freescale Semiconductor

ISBN: (纸本)9781595931610

We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application's binary are competitive with partitioning at the C source code level. While such competitiveness has been shown previously for standard benchmark suites involving smaller or unoptimized applications, the case study instead focuses on a complete 16,000-line highly-optimized commercial-grade application, namely an H.264 video decoder. The several month study revealed that binary partitioning was indeed competitive, achieving nearly identical 2.5x speedups as source level partitioning, compared to a standard microprocessor. Furthermore, the study revealed that several simple C-level coding modifications, including pass by value-return, function specialization, algorithmic specialization, hardware-targeted reimplementation, global array elimination, hoisting and sinking of error code, and conversion to explicit control flow, could lead to improved application speedups approaching 7x for both source level and binary level partitioning.

关键词： synthesis binaries H.264 hardware/software partitioning FPGA embedded systems

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Rappit: framework for synthesis of host-assisted scripting engines for adaptive embedded systems 05

Rappit: framework for synthesis of host-assisted scripting e...

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Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Jiwon Hahn Qiang Xie Pai H. Chou University of California Irvine CA

ISBN: (纸本)9781595931610

Scripting is a powerful, high-level, cross-platform, dynamic, easy way of composing software modules as black boxes. Unfortunately, the high runtime overhead has prevented scripting from being widely adopted in embedded applications. This work proposes to overcome these obstacles by synthesizing light-weight, host-assisted scripting engines for embedded systems. The result is dramatically shortened development cycle due to the much higher-level abstraction, interactive access and dynamic reconfigurability, robust in-field software upgradability, and compact code size. This framework has been successfully applied to ultra low-power sensor nodes with under 10KB of program memory to high-performance platforms with fast Ethernet.

关键词： adaptive systems scripting software synthesis

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FPGA HW/SW codesign Approach for Real-time Image Processing Using HLS

FPGA HW/SW Codesign Approach for Real-time Image Processing ...

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Communications, Control systems and Signal Processing (CCSSP), 2020 1st international conference on

作者： Mohamed Salah AZZAZ Abdelmadjd MAALI Redouane KAIBOU Ibrahim KAKOUCHE Mohamed SAAD Hocine HAMIL Ecole Militaire Polytechnique Laboratoire SEN Algiers Algeria Mouloud Mammeri University LAMPA Laboratory Tizi-Ouzou Algeria

ISBN: (数字)9781728158358

ISBN: (纸本)9781728158365

Real-time constraint is one of the most common challenges found in many critical embedded applications, namely image and video processing. However, software tools such as Matlab and general purpose microprocessor are not suitable for deals with such a problem. Recently, FPGA reconfigurable circuit with its HLS software tools is become a very promising technology to be widely used in many applications encompassing all aspects and requirements of embedded system. This paper presents the implementation of morphological image operation including dilation, erosion and linear filtering. The implementation method is based on hardware/software (HW/SW) codesign approach using High Level synthesis (HLS) tools, Xilinx Vivado 15.2 and SDK 15.2. Zedboard FPGA platform with Zynq device is used for this work in which is connected to a PC through an Ethernet link. Captured image by Webcam is transmitted to the FPGA for processing and will be then returned to the PC to be displayed on the IHM interface, in real-time. Experimental results demonstrate the feasibility of the proposed approach and it can be extended for other applications.

关键词： Field programmable gate arrays Tools IP networks Convolution hardware Real-time systems Program processors

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A codesign Tool for High Level Systhesis of Vision Models on FPL

A Codesign Tool for High Level Systhesis of Vision Models on...

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international conference on Field Programmable Logic and Applications

作者： Antonio Martinez Leonardo Reynery Francisco Pelayo Christian Morillas Samuel Romero Department of Computing Technology University of Alicante Spain Department of Electronics Polytechnic of Torino Italy Department of Computer Engineering University of Granada Spain Department of Computer Sciences University of Jaen Spain

This paper presents a synthesis tool for the automatic translation and optimization of bioinspired vision models into a FPL implementation. The software allows functional simulation and high level specification of the model, and produces a data-flow model using VHDL, which is synthesizable with different lower-level synthesis tools and for various FPGA technologies. The proposed design platform extends the features of the codesign environment CodeSimulink for implementing visual processing systems, starting from purely functional specifications. An optimization strategy based on the calculation of the Pareto front is also introduced to perform a multi-objective minimization of both, the circuit area and the root mean square of the computation error. Performance measurements for the FPL implementation of an example retina-like vision model on a FPGA-based PCI board are provided

关键词： Mathematical model Computer vision Field programmable gate arrays Computational modeling Power system modeling hardware Real time systems Filters Design engineering Knowledge engineering

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A Novel Deadlock Avoidance Algorithm and Its hardware Implementation 04

A Novel Deadlock Avoidance Algorithm and Its Hardware Implem...

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Proceedings of the international conference on hardware/software codesign and system synthesis: 2004

作者： Jaehwan Lee Vincent John Mooney III Georgia Institute of Technology

ISBN: (纸本)9781581139372

This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provides a mechanism for very fast and automatic deadlock avoidance in MultiProcessor system-on-a-Chip (MPSoC) with multiple (e.g., 10) processing elements and multiple (e.g., 40) resources. The DAU avoids deadlock by not allowing any grant or request that leads to a deadlock. In case of livelock, the DAU asks one of the processes involved in the livelock to release resource(s) so that the livelock can also be resolved. We simulated two realistic examples that can benefit from the DAU, and demonstrated that the DAU not only avoids deadlock in a few clock cycles but also achieves a 37% speed-up of application execution time over avoiding deadlock in software. Finally, the SoC area overhead due to the DAU is small, under 0.01% in our example.

关键词： Algorithms

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ReSQM: Accelerating Database Operations Using ReRAM-Based Content Addressable Memory

ReSQM: Accelerating Database Operations Using ReRAM-Based Co...

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作者： Li, Huize Jin, Hai Zheng, Long Liao, Xiaofei National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

The huge amount of data enforces great pressure on the processing efficiency of database systems. By leveraging the in-situ computing ability of emerging nonvolatile memory, processing-in-memory (PIM) technology shows great potential in accelerating database operations against traditional architectures without data movement overheads. In this article, we introduce ReSQM, a novel ReCAM-based accelerator, which can dramatically reduce the response time of database systems. The key novelty of ReSQM is that some commonly used database queries that would be otherwise processed inefficiently in previous studies can be in-situ accomplished with massively high parallelism by exploiting the PIM-enabled ReCAM array. ReSQM supports some typical database queries (such as SELECTION, SORT, and JOIN) effectively based on the limited computational mode of the ReCAM array. ReSQM is also equipped with a series of hardware-algorithm co-designs to maximize efficiency. We present a new data mapping mechanism that allows enjoying in-situ in-memory computations for SELECTION operating upon intermediate results. We also develop a count-based ReCAM-specific algorithm to enable the in-memory sorting without any row swapping. The relational comparisons are integrated for accelerating inequality join by making a few modifications to the ReCAM cells with negligible hardware overhead. The experimental results show that ReSQM can improve the (energy) efficiency by $611\times $ ( $193\times $ ), $19\times $ ( $17\times $ ), $59\times $ ( $43\times $ ), and $307\times $ ( $181\times $ ) in comparison to a 10-core Intel Xeon E5-2630v4 processor for SELECTION, SORT, equi-join, and inequality join, respectively. In contrast to state-of-the-art CMOS-based CAM, GPU, FPGA, NDP, and PIM solutions, ReSQM can also offer $2.2\times 39\times $ speedups. © 1982-2012 IEEE.

关键词： Query languages

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An efficient hardware design for cerebellar models using approximate circuits: special session paper 17

An efficient hardware design for cerebellar models using app...

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Proceedings of the Twelfth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Honglan Jiang Leibo Liu Jie Han University of Alberta Edmonton AB Canada Tsinghua University Beijing China

ISBN: (纸本)9781450351850

The superior controllability of the cerebellum has motivated extensive interest in the development of computational cerebellar models. Many models have been applied to the motor control and image stabilization in robots. Often computationally complex, cerebellar models have rarely been implemented in dedicated hardware. Here, we propose an efficient hardware design for cerebellar models using approximate circuits with a small area and a low power. Leveraging the inherent error tolerance in the cerebellum, approximate adders and multipliers are carefully evaluated for implementations in an adaptive filter based cerebellar model to achieve a good tradeoff in accuracy and hardware usage. A saccade system, whose vestibulo-ocular reflex (VOR) is controlled by the cerebellum, is simulated to show the applicability and effectiveness of the proposed design. Simulation results show that the approximate cerebellar circuit achieves a similar accuracy as an exact implementation, but it saves area by 29.7% and power by 37.3%.

关键词： multiplier cerebellar model approximate circuits adder

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