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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

共 853 条记录，以下是781-790 订阅

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A Novel Deadlock Avoidance Algorithm and Its hardware Implementation 04

A Novel Deadlock Avoidance Algorithm and Its Hardware Implem...

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Proceedings of the international conference on hardware/software codesign and system synthesis: 2004

作者： Jaehwan Lee Vincent John Mooney III Georgia Institute of Technology

ISBN: (纸本)9781581139372

This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provides a mechanism for very fast and automatic deadlock avoidance in MultiProcessor system-on-a-Chip (MPSoC) with multiple (e.g., 10) processing elements and multiple (e.g., 40) resources. The DAU avoids deadlock by not allowing any grant or request that leads to a deadlock. In case of livelock, the DAU asks one of the processes involved in the livelock to release resource(s) so that the livelock can also be resolved. We simulated two realistic examples that can benefit from the DAU, and demonstrated that the DAU not only avoids deadlock in a few clock cycles but also achieves a 37% speed-up of application execution time over avoiding deadlock in software. Finally, the SoC area overhead due to the DAU is small, under 0.01% in our example.

关键词： Algorithms

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Development of a hardware system for Digital Control of a Boost DC/DC Converter

Development of a Hardware System for Digital Control of a Bo...

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international conference on Information Technologies (InfoTech)

作者： Ivan Hristov Nikolay Hinov Department of Electronics Faculty of Electronic Engineering and Technologies Technical University of Sofia Sofia Bulgaria

ISBN: (数字)9798350365689

ISBN: (纸本)9798350365696

The work presents a hardware system for the synthesis of digital control of a Boost DC/DC converter, based on a microcontroller. The algorithm of work and successive steps are considered, as well as examples that implement selected control laws. Thus, the developed system is useful both from the point of view of power electronics education and for the needs of designers involved in the prototyping of specific power devices. The main advantage of the proposed system is its flexibility and compatibility with mathematical software, which makes it applicable in combination with the model-based design of power electronic devices.

关键词： Digital control Voltage measurement Microcontrollers Digital systems software algorithms Prediction algorithms software hardware Power electronics Time factors

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Implementation of Euclidean Clustering for Object Detection Using 3D LiDAR in an Autonomous Vehicle Prototype with Embedded system and ROS

Implementation of Euclidean Clustering for Object Detectio...

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international conference on Information Technology and systems, ICITS 2024

作者： Idrovo-Berrezueta, Paul S. Dutan-Sanchez, Denys A. Valladolid-Quitoisaca, Juan D. Ortiz-Gonzalez, Juan P. GIIT Universidad Politécnica Salesiana Cuenca Ecuador

ISBN: (纸本)9783031542558

In the pursuit of advancing autonomous driving and automation across various domains, precise obstacle detection stands as an essential feature. Leveraging LiDAR (Light Detection and Ranging) technology, renowned for its ability to provide intricate three-dimensional environmental insights, this article delves into a comprehensive methodology for obstacle detection and tracking. This methodology encompasses key aspects including point cloud preprocessing, segmentation, clustering, and obstacle tracking, all of which collectively contribute to a meticulous and robust perception framework. The article also underscores the merits of deploying a functional prototype and harnessing the potential of the Robot Operating system (ROS) to bolster environmental perception, enabling real-time testing and experimentation. The synthesis of these components not only substantiates the effectiveness of our approach but also highlights its potential implications in enhancing safety and decision-making within autonomous and automated systems. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2024.

关键词： Robot Operating system

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An efficient hardware design for cerebellar models using approximate circuits: special session paper 17

An efficient hardware design for cerebellar models using app...

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Proceedings of the Twelfth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Honglan Jiang Leibo Liu Jie Han University of Alberta Edmonton AB Canada Tsinghua University Beijing China

ISBN: (纸本)9781450351850

The superior controllability of the cerebellum has motivated extensive interest in the development of computational cerebellar models. Many models have been applied to the motor control and image stabilization in robots. Often computationally complex, cerebellar models have rarely been implemented in dedicated hardware. Here, we propose an efficient hardware design for cerebellar models using approximate circuits with a small area and a low power. Leveraging the inherent error tolerance in the cerebellum, approximate adders and multipliers are carefully evaluated for implementations in an adaptive filter based cerebellar model to achieve a good tradeoff in accuracy and hardware usage. A saccade system, whose vestibulo-ocular reflex (VOR) is controlled by the cerebellum, is simulated to show the applicability and effectiveness of the proposed design. Simulation results show that the approximate cerebellar circuit achieves a similar accuracy as an exact implementation, but it saves area by 29.7% and power by 37.3%.

关键词： multiplier cerebellar model approximate circuits adder

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ReSQM: Accelerating Database Operations Using ReRAM-Based Content Addressable Memory

ReSQM: Accelerating Database Operations Using ReRAM-Based Co...

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作者： Li, Huize Jin, Hai Zheng, Long Liao, Xiaofei National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

The huge amount of data enforces great pressure on the processing efficiency of database systems. By leveraging the in-situ computing ability of emerging nonvolatile memory, processing-in-memory (PIM) technology shows great potential in accelerating database operations against traditional architectures without data movement overheads. In this article, we introduce ReSQM, a novel ReCAM-based accelerator, which can dramatically reduce the response time of database systems. The key novelty of ReSQM is that some commonly used database queries that would be otherwise processed inefficiently in previous studies can be in-situ accomplished with massively high parallelism by exploiting the PIM-enabled ReCAM array. ReSQM supports some typical database queries (such as SELECTION, SORT, and JOIN) effectively based on the limited computational mode of the ReCAM array. ReSQM is also equipped with a series of hardware-algorithm co-designs to maximize efficiency. We present a new data mapping mechanism that allows enjoying in-situ in-memory computations for SELECTION operating upon intermediate results. We also develop a count-based ReCAM-specific algorithm to enable the in-memory sorting without any row swapping. The relational comparisons are integrated for accelerating inequality join by making a few modifications to the ReCAM cells with negligible hardware overhead. The experimental results show that ReSQM can improve the (energy) efficiency by $611\times $ ( $193\times $ ), $19\times $ ( $17\times $ ), $59\times $ ( $43\times $ ), and $307\times $ ( $181\times $ ) in comparison to a 10-core Intel Xeon E5-2630v4 processor for SELECTION, SORT, equi-join, and inequality join, respectively. In contrast to state-of-the-art CMOS-based CAM, GPU, FPGA, NDP, and PIM solutions, ReSQM can also offer $2.2\times 39\times $ speedups. © 1982-2012 IEEE.

关键词： Query languages

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AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress 18

AMVP - a high performance virtual platform using parallel sy...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Jan Henrik Weinstock Róbert Lajos Bücs Florian Walbroel Rainer Leupers Gerd Ascheid RWTH Aachen University

ISBN: (纸本)9781538655627

This paper presents AMVP - a systemC based simulator for ARM multicore platforms designed as a tool for early SW development during platform bring-up. It uses a parallel systemC simulation approach to counter the performance slowdown incurred when simulating multi-processor designs. AMVP is sufficiently detailed to support running and debugging unmodified SW images of popular benchmark applications and modern OS kernels like Linux.

关键词： parallel systemC simulation parallel discrete event simulation electronic system level

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Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design 05

Service dependency graph: an efficient model for hardware/so...

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Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Adriano Sarmento Lobna Kriaa Arnaud Grasset Mohamed-Wassim Youssef Aimen Bouchhima Frederic Rousseau Wander Cesario Ahmed Amine Jerraya TIMA Laboratory CEDEX France

ISBN: (纸本)9781595931610

Complex systems-on-chip are designed by interconnecting pre-designed hardware (HW) and software (SW) components. During the design cycle, a global model of the SoC may be composed of HW and SW models at different abstraction levels. Designing HW/SW interfaces to interconnect SoC components is a source of design bottlenecks. This paper describes a service-based model enabling systematic design and co-simulation of HW/SW interfaces for SoC design. This model, called Service dependency graph (SDG) allows modeling of complex and application-specific interfaces. We present also a model generator that can automatically build HW/SW interfaces based on service and resource requirements described by the SDG. This approach has been applied successfully on the design of an MPEG-4 encoder. Additionally the SDG seems to be an excellent intermediate representation for the design automation of HW/SW interfaces.

关键词： service-based model systems-on-chip hardware/software interfaces interface design automation

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APECS: An AADL and polychrony based embedded computing system design environment with an elevator control case study

APECS: An AADL and polychrony based embedded computing syste...

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Matthew Anderson Sandeep K. Shukla Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA

ISBN: (纸本)9781479909049

Architecture Analysis and Design Language (AADL) is a standard that originated in the avionics domain, but is now being used in avionics and other critical distributed real-time embedded system design. AADL provides a formal notation and semantics for capturing an entire distributed platform architecture (hardware components, protocols, and software architecture annotated with properties including real-time measures). The software architecture captures the location and structure of processes, threads, and the data and control flow specifications. The behavior of the processes/threads/subprograms are provided via a native state machine language or via a behavioral annex. Schedulability, performance, and other system level properties can be analyzed using various tools. Even code synthesis - targeting the formally described platform components and middleware can be enabled if the threads/processes can be behaviorally specified. In this paper, we describe our methodology and a design environment both named APECS. APECS is meant for enabling an end-to-end distributed real-time embedded system design which integrates a number of existing tools, and our own polychronous language based specification language MRICDF, and the corresponding synthesis methodology. While the environment is in an advanced stage of development, we illustrate the architecture of the design environment, and illustrate the methodology through a non-trivial case study. The case study uses APECS methodology and tools in developing the distributed control for a 4 bank elevator system in a 5 story building. We posit this paper as a methodology and tool paper and it is written in a tutorial spirit rather than a paper describing new theories or algorithms.

关键词： Analytical models Real-time systems Program processors Ports (Computers) Computer architecture Standards

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Novel architecture for loop acceleration: a case study 05

Novel architecture for loop acceleration: a case study

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Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Seng Lin Shee Sri Parameswaran Newton Cheung University of New South Wales Sydney Australia

ISBN: (纸本)9781595931610

In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this architecture. To illustrate the advantages of this approach, we investigate a JPEG encoding algorithm and accelerate one of its loop by implementing it in a coprocessor. We contrast the acceleration by implementing the critical segment as two different coprocessors and a set of customized instructions. The two different coprocessor approaches are: a high-level synthesis (HLS) approach; and a custom coprocessor approach. The HLS approach provides a faster method of generating coprocessors. We show that a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, compared to 1.58x for the HLS approach and 1.33x for the customized instruction approach compared with just the main processor. Respective energy savings within the loop are 57%, 28% and 19%.

关键词： ASIP architecture coprocessor latency hiding hardware/software partitioning loop optimization tightly coupled loop acceleration loop pipelining

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A low-cost and low-power multi-standard video encoder 03

A low-cost and low-power multi-standard video encoder

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Proceedings of the 1st IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： R. Peset Llopis R. Sethuraman C. Alba Pinto H. Peters S. Maul M. Oosterhuis Philips Research Laboratories Eindhoven The Netherlands

ISBN: (纸本)9781581137422

Video encoders are an important IP block in mobile multimedia systems. In this paper, we describe a low-cost low-power multi-standard (MPEG4, JPEG, and H.263) video/image encoder. The low-cost and low-power aspects are achieved by the right choice of algorithms and architectures. In the algorithm front, an embedded compression technique for reducing the size of loop memory has enabled a single-chip low-cost realization of the encoder. In the architectural front, an efficient hardware-software partitioning has contributed to the design of a low-power encoder. Further, the hardware components that accelerate the kernels of encoding are implemented as application specific instruction-set processors (ASIPs) thereby providing flexibility to address multi-standard encoding. The power and area estimates for the encoder for [email protected] in 0.18um CMOS technology are 30mW and 20mm2 respectively including the loop memory.

关键词： multi-standard low-cost hardware/software partitioning low-power video encoder ASIPs

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