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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

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Novel architecture for loop acceleration: a case study 05

Novel architecture for loop acceleration: a case study

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Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Seng Lin Shee Sri Parameswaran Newton Cheung University of New South Wales Sydney Australia

ISBN: (纸本)9781595931610

In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this architecture. To illustrate the advantages of this approach, we investigate a JPEG encoding algorithm and accelerate one of its loop by implementing it in a coprocessor. We contrast the acceleration by implementing the critical segment as two different coprocessors and a set of customized instructions. The two different coprocessor approaches are: a high-level synthesis (HLS) approach; and a custom coprocessor approach. The HLS approach provides a faster method of generating coprocessors. We show that a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, compared to 1.58x for the HLS approach and 1.33x for the customized instruction approach compared with just the main processor. Respective energy savings within the loop are 57%, 28% and 19%.

关键词： ASIP architecture coprocessor latency hiding hardware/software partitioning loop optimization tightly coupled loop acceleration loop pipelining

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Development of Testing Method for FPGA-Based system

Development of Testing Method for FPGA-Based System

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international conference on Modern Problems of Radio Engineering, Telecommunications and Computer Science

作者： Roman Diachok Halyna Klym Oleksand Stepanov Specialized Computer Systems Dpt. Lviv Polytechnic National University Lviv Ukraine

ISBN: (数字)9798331520564

ISBN: (纸本)9798331520571

High-Level synthesis (HLS) Tools help engineers deal with the challenges of building complex systems that use reconfigurable technologies. In addition, HLS serves as a precursor to well-established methods in the software industry, such as Test-Driven Development (TDD), in the development process of hardware components of an embedded system. However, the assistance offered by the HLS validation tools could be strengthened and targeted at the early stages of project development. This paper describes a hardware testing framework as a means to quickly evaluate the capabilities of embedded components using a unit testing paradigm, leading to TDD implementation on reconfigurable hardware.

关键词： Industries Embedded systems Protocols Market research hardware software Telecommunications Field programmable gate arrays Testing software development management

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Model driven engineering for SoC co-design

Model driven engineering for SoC co-design

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Annual IEEE Northeast Workshop on Circuits and systems (NEWCAS)

作者： J. Dekeyser P. Boulet P. Marquet S. Meftali Laboratoire dInformatique Fondamentale de Lille Université des Sciences et Technologies de Lille Villeneuve d'Ascq France

SoC co-design requires to master a lot of different abstraction levels, different simulation techniques, different synthesis tools. Due to the evolution of the technologies, the best one is the one to come. Evolution of an embedded system both hardware and software, is not simple. The business logic has to be kept and the technical aspect has to be thrown. To improve the permanence of system on chip we have to abstract from the technical concerns. Model driven engineering (MDE) proposes a separation of concerns: application and technical concerns. The use of a modeling standard can capitalize system descriptions and improve system evolution and integration. A particular aspect of MDE concerns model transformations and code generation. At this level, the basic model driven architecture pattern involves the definition of a platform-independent model (PIM) and its automated mapping to one or more platform-specific models (PSMs). By defining different PIM and PSM dedicated to embedded systems, we show the benefits of using the MDE approach in system on chip codesign. From UML 2.0 profiles to systemC or VHDL codes, the same model transformation engine is used with different rules expressed in XML.

关键词： Model driven engineering Embedded system system-on-a-chip hardware Embedded software Logic Application software Unified modeling language Engines XML

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Keynote: cellular handset technology system requirements and integration trends 04

Keynote: cellular handset technology system requirements and...

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Proceedings of the 2nd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Sven Mattisson Ericsson Mobile Platforms AB Lund Sweden

ISBN: (纸本)9781581139372

In ten years the cellular telephone has evolved from a tool for the professional to an indispensable consumer product with a very high market penetration. At the same time, the handset cost, weight, and standby time have been reduced by more than a factor of ten. These factors have been critical for the success story of the mobile *** technical aspects behind the rapid handset evolution are discussed. In particular, what advances in the radio architecture, for example the zero-IF GSM receiver,the baseband (CMOS) technology, andthe radio system design areasSW-DSP-digital-RF partitioning,linear multi-mode modulation with high linearity requirements,digital leakage issues, andpower consumption limitations in multimedia handsets are discussed with future generation handsets in mind.

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The design of a smart imaging core for automotive and consumer applications: a case study 05

The design of a smart imaging core for automotive and consum...

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Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Wido Kruijtzer Winfried Gehrke Victor Reyes Ghiath Alkadi Thomas Hinz Jorn Jöchalsky Bruno Steux Philips Research The Netherlands Philips Semiconductors Hamburg Germany University of Las Palmas GC Spain University of Hannover Germany École des Mines de Paris France

ISBN: (纸本)9781595931610

This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two specific hardware blocks for image processing: a smart imaging coprocessor and an enhanced motion estimator. Both coprocessors have been designed using high-level synthesis tools taking the C programming language as a starting point. The resulting RTL code of each coprocessor has been synthesized and verified on an FPGA board. Two automotive and two mobile smart imaging applications are mapped onto the resulting smart imaging core. This mapping process of the original C++ applications onto the smart imaging core is also presented in this paper.

关键词： system level design image processing

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HW/SW codesign for embedded telecom systems

HW/SW codesign for embedded telecom systems

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： S. Antoniazzi A. Balboni W. Fornaciari D. Sciuto CEFRIEL Milano Italy Central Research Labs CLTE ITALTEL-SIT Milano Italy Dip. Elettronica e Inform Politecnico di Milano Milano Italy

The aim of this paper is to define an approach, tailored for control-oriented applications, to manage system cospecification, high-level partitioning, hw/sw tradeoffs and cosynthesis. Our research effort focuses on fulfilling the goal of linking high-level specifications to efficient and cost-effective hw/sw implementations by investigating techniques such as synchronous cospecification styles, direct machine code generation as well as exploiting the capability of commercial VHDL synthesis tools.< >

关键词： Telecommunications Application specific integrated circuits hardware Design automation Application software Neutron spin echo Joining processes Logic design Microprogramming Project management

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Exploring fast and slow memories in HMP core types: work-in-progress 17

Exploring fast and slow memories in HMP core types: work-in-...

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Proceedings of the Twelfth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Bryan Donyanavard Amir Mahdi Hosseini Monazzah Tiago Mück Nikil Dutt University of California Sharif University of Technology

ISBN: (纸本)9781450351850

Studies have shown memory and computational needs vary independently across applications. Recent work has explored using hybrid memory technology (SRAM+NVM) in on-chip memories of multicore processors (CMPs) to support the varied needs of diverse workloads. Such works suggest architectural modifications that require supplemental management in the memory hierarchy. Instead, we propose to deploy hybrid memory in a manner that integrates seamlessly with the existing heterogeneous multicore (HMP) architectural model, and therefore does not require any architectural modification, simply the integration of different memory technologies on-chip. We evaluate platforms with a combination of fast (SRAM cache) and slow (STT-MRAM cache) core-types for mobile workloads.

关键词： SPM scratchpad memory hardware/software memory management many-core architectures virtualization

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SOMA: a tool for synthesizing and optimizing memory accesses in ASICs 05

SOMA: a tool for synthesizing and optimizing memory accesses...

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Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Girish Venkataramani Tiberiu Chelcea Seth Copen Goldstein Tobias Bjerregaard Carnegie Mellon University Pittsburgh PA TU Denmark Lyngby Denmark

ISBN: (纸本)9781595931610

Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the MAN architecture. Depending on the parallelism profile, the MAN may be optimized for latency, throughput or both. The optimized MAN is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance.

关键词： high-level synthesis memory synthesis

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Efficient Gait Trajectory Prediction Method Based on Soft Constraint Weighted Template Matching: Work-in-Progress

Efficient Gait Trajectory Prediction Method Based on Soft Co...

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Proceedings of the 2023 international conference on hardware/software codesign and system synthesis

作者： Xing Liu Yifan Liu Xingjun Wang Shenzhen International Graduate School Tsinghua University Shenzhen Guangdong China

ISBN: (纸本)9798400702891

Embedded systems in exoskeletons and wearable rehabilitation devices require efficient monitoring of human gait with stringent demands for real-time and reliable performance. Gait trajectory prediction enables full-process perception of future gait patterns. The template matching approach is a promising algorithm for gait trajectory prediction. However, it has challenges in terms of template selection and dynamic stability. We developed DTW-KM Template Selection Method using the DTW distance matrix and K-means to find trajectories with generality and diversity as candidate templates. In addition, we use a matching method combining soft constraints and quadratic weighting, named ScW Template Matching Method. it can balance timeliness, stability and flexibility, and suppress gait phase and trajectory oscillations. Preliminary experimental results show that our method achieves stable prediction of 0.5--1s gait using efficient inference on embedded devices.

关键词： real time trajectory prediction template matching soft constraint

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A chip-level security framework for assessing sensor data integrity: work-in-progress 18

A chip-level security framework for assessing sensor data in...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Taimour Wehbe Vincent J. Mooney David C. Keezer Georgia Institute of Technology

ISBN: (纸本)9781538655627

The continuously increasing inter-connectivity of sensor nodes that form the basis of the Internet-of-Things results in new avenues of attack exploitable by adversaries to maliciously modify data captured by these nodes. In this work, we present a framework for detecting malicious hardware alterations that attempt to attack state-of-the-art microchips that form these sensor nodes. Specifically, we focus on extremely small hardware Trojans (HTs) that attempt to modify sensor data right away as the data is received on a state-of-the-art chip fabricated in an untrusted facility. We present a dual-chip approach composed of an untrusted state-of-the-art prover chip and a trusted verifier chip, where the verifier continuously challenges the prover at run-time to ensure correct operation and assess the integrity of the captured data. Our preliminary analysis of the proposed mechanism shows that HT attacks anywhere on the untrusted state-of-the-art chip are detected and flagged preventing maliciously altered data to be transmitted out of the sensor node.

关键词： embedded systems security hardware trojans malicious design modifications sensor networks data integrity security in hardware hardware attacks and countermeasures

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