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检索条件"任意字段=2024 International Conference on Hardware/Software Codesign and System Synthesis"

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On leveraging approximations for exact system-level design space exploration: work-in-progress 18

On leveraging approximations for exact system-level design s...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Kai Neubauer Christian Haubelt Philipp Wanko Torsten Schaub University of Rostock Germany University of Potsdam Germany

ISBN: (纸本)9781538655627

In order to find good design points for embedded systems, an efficient exploration of the design space is imperative. The ever-increasing complexity of embedded systems, however, results in a deterioration of the overall exploration performance. The DSE essentially consists of two parts: (1) the search for feasible solutions and (2) the evaluation of found feasible solutions. While the search has been massively improved by ASPmT-based strategies, the evaluation emerges as the main bottleneck. Tragically, evaluating bad solutions takes as much time as evaluating good ones. Hence, in this paper we study the utilization of approximations in the evaluation process integrated in an ASPmT-based DSE to identify bad solutions more quickly while still retaining the exact Pareto-front.

关键词： system-level design approximation design space exploration

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Keynote: cellular handset technology system requirements and integration trends 04

Keynote: cellular handset technology system requirements and...

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Proceedings of the 2nd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Sven Mattisson Ericsson Mobile Platforms AB Lund Sweden

ISBN: (纸本)9781581139372

In ten years the cellular telephone has evolved from a tool for the professional to an indispensable consumer product with a very high market penetration. At the same time, the handset cost, weight, and standby time have been reduced by more than a factor of ten. These factors have been critical for the success story of the mobile *** technical aspects behind the rapid handset evolution are discussed. In particular, what advances in the radio architecture, for example the zero-IF GSM receiver,the baseband (CMOS) technology, andthe radio system design areasSW-DSP-digital-RF partitioning,linear multi-mode modulation with high linearity requirements,digital leakage issues, andpower consumption limitations in multimedia handsets are discussed with future generation handsets in mind.

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SOMA: a tool for synthesizing and optimizing memory accesses in ASICs 05

SOMA: a tool for synthesizing and optimizing memory accesses...

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Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Girish Venkataramani Tiberiu Chelcea Seth Copen Goldstein Tobias Bjerregaard Carnegie Mellon University Pittsburgh PA TU Denmark Lyngby Denmark

ISBN: (纸本)9781595931610

Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the MAN architecture. Depending on the parallelism profile, the MAN may be optimized for latency, throughput or both. The optimized MAN is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance.

关键词： high-level synthesis memory synthesis

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Efficient Gait Trajectory Prediction Method Based on Soft Constraint Weighted Template Matching: Work-in-Progress

Efficient Gait Trajectory Prediction Method Based on Soft Co...

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Proceedings of the 2023 international conference on hardware/software codesign and system synthesis

作者： Xing Liu Yifan Liu Xingjun Wang Shenzhen International Graduate School Tsinghua University Shenzhen Guangdong China

ISBN: (纸本)9798400702891

Embedded systems in exoskeletons and wearable rehabilitation devices require efficient monitoring of human gait with stringent demands for real-time and reliable performance. Gait trajectory prediction enables full-process perception of future gait patterns. The template matching approach is a promising algorithm for gait trajectory prediction. However, it has challenges in terms of template selection and dynamic stability. We developed DTW-KM Template Selection Method using the DTW distance matrix and K-means to find trajectories with generality and diversity as candidate templates. In addition, we use a matching method combining soft constraints and quadratic weighting, named ScW Template Matching Method. it can balance timeliness, stability and flexibility, and suppress gait phase and trajectory oscillations. Preliminary experimental results show that our method achieves stable prediction of 0.5--1s gait using efficient inference on embedded devices.

关键词： real time trajectory prediction template matching soft constraint

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Design for testability: today and in the future

Design for testability: today and in the future

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international conference on VLSI Design

作者： T.W. Williams IBM Technology Products Boulder CO USA

Summary form only given. The author reviews the current techniques with a particular emphasis on today's Scan Designs. This entails distinguishing the differences between scan techniques, since all scans are not created equal! From this point the Testability Standards are discussed; these include the Boundary Scan activities and the Analog activities. Fault models are taking on more robust attributes, since the Stuck-At-Fault is necessary but not sufficient in today's technologies. The Delay Fault models are discussed with a comparison between a model which increases exponentially with gate count (Path Delay Fault) and one which increases linearly with gate count (Gate Delay Fault). Clearly, self-test is taking on an ever more important role which impacts both manufacturing testing and field system testing. The popular self-testing design techniques are shown. The interaction of testing and synthesis is discussed with a view on delay. Finally, the role of testing is explored in the new design environments which includes hardware and software codesign.

关键词： Design for testability Automatic testing Built-in self-test Delay Circuit testing Computer Society Books Logic testing system testing Very large scale integration

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CRAMES: compressed RAM for embedded systems 05

CRAMES: compressed RAM for embedded systems

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Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Lei Yang Robert P. Dick Haris Lekatsas Srimat Chakradhar Northwestern University Evanston IL NEC Laboratories America Princeton NJ

ISBN: (纸本)9781595931610

Memory is a scarce resource in many embedded systems. Increasing memory often increases packaging and cooling costs, size, and energy consumption. This paper presents CRAMES, an efficient software-based RAM compression technique for embedded systems. The goal of CRAMES is to dramatically increase effective memory capacity without hardware design changes, while maintaining high performance and low energy consumption. To achieve this goal, CRAMES takes advantage of an operating system's virtual memory infrastructure by storing swapped-out pages in compressed format. It dynamically adjusts the size of the compressed RAM area, protecting applications capable of running without it from performance or energy consumption penalties. In addition to compressing working data sets, CRAMES also enables efficient in-RAM filesystem compression, thereby further increasing RAM capacity. CRAMES was implemented as a loadable module for the Linux kernel and evaluated on a battery-powered embedded system. Experimental results indicate that CRAMES is capable of doubling the amount of RAM available to applications. Execution time and energy consumption for a broad range of examples increase only slightly, by averages of 0.35% and 4.79%. In addition, this work identifies the software-based compression algorithms that are most appropriate for low-power embedded systems.

关键词： memory embedded system compression

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The Integration and Testing Procedures for the AcubeSAT Nanosatellite’s software

The Integration and Testing Procedures for the AcubeSAT Nano...

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international conference on synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

作者： Antonios Keremidis Stylianos Tzelepis Alkis Hatzopoulos SpaceDot Greece Aristotle University of Thessaloniki Greece National Technical University of Athens Greece Dept. of Electrical and Computer Eng Electronics Lab AUTh

ISBN: (数字)9798350351927

ISBN: (纸本)9798350351934

The AcubeSAT space mission, a collaborative effort within the Fly Your Satellite! 3 program of the European Space Agency (ESA) Education Office and SpaceDot, features unique payload requirements aimed at exploring the effects of radiation and microgravity on eukaryotic cells in Low Earth Orbit (LEO). To address these specialized needs, custom Printed Circuit Board (PCB)s were developed, bypassing off-the-shelf solutions for greater efficiency of the mission and cost-effectiveness. However, this decision introduced a notable challenge: the development of complex system software to ensure the successful execution of all mission phases and the secure transmission of scientific data back to Earth. In this paper, we report on the status of the development and validation processes for the satellite software in its current state, on custom hardware to ensure mission success.

关键词： Satellites Space missions European Space Agency Low earth orbit satellites Static analysis software hardware Standards Testing software engineering

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Development of Algorithmic and software hardware for the Control system of a Bionic Walking Robot

Development of Algorithmic and Software Hardware for the Con...

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international Russian Automation conference (RusAutoCon)

作者： Daniyar A. Wolf Rinat R. Galin Yaroslav A. Turovsky Laboratory of Cyber-Physical Systems V.A. Trapeznikov Institute of Control Sciences of Russian Academy of Sciences Moscow Russia

ISBN: (数字)9798350349818

ISBN: (纸本)9798350349825

The paper considers the topical issue of the development of bionic walking robots of the Felida class. Information is provided on the research work carried out and the experimental design development of an interactive bionic robot. The purpose of this work is to develop approaches to creating a mobile robotic system that moves in steps, which allows it to move through an unprepared area in advance. The object of the study is a bionic walking robot developed by the authors. The multilevel structure of the walking robot control system is presented in this paper. The analysis of the results of the study of the biological characteristics of felid was carried out and the control elements subject to bionic synthesis were identified. The paper reflects the comparative characteristics of the developed bionic walking robot and its analogue. There is a model of a bionic walking robot and the kinematics of its supports. The software model of the robot consider interaction between control and actuators of the robot on the ROS platform, as part of the links between publisher and subscriber nodes. The hardware architecture organized according to the principle of a two-level control architecture. The first hardware and software level (the control body of the first level) and the second level implements the interface for interaction of application services with the subsystem of the first level. This paper can be useful for both educational and research tasks in the field of developing bionic walking robots.

关键词： Legged locomotion Biological system modeling software algorithms Robot control Computer architecture Open systems Maintenance engineering software hardware Robots

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Edge-TM: Exploiting transactional memory for error tolerance and energy efficiency

Edge-TM: Exploiting transactional memory for error tolerance...

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ACM Transactions on Embedded Computing systems

作者： Papagiannopoulou, Dimitra Marongiu, Andrea Moreshet, Tali Herlihy, Maurice Bahar, R. Iris Department of Electrical and Computer Engineering University of Massachusetts Lowell LowellMA01854 United States Department of Information Technology and Electrical Engineering ETH Zurich Zurich8092 Switzerland College of Engineering Boston University BostonMA02215 United States Department of Computer Science Brown University ProvidenceRI02912 United States School of Engineering Brown University ProvidenceRI02912 United States

Scaling of semiconductor devices has enabled higher levels of integration and performance improvements at the price of making devices more susceptible to the effects of static and dynamic variability. Adding safety margins (guardbands) on the operating frequency or supply voltage prevents timing errors, but has a negative impact on performance and energy consumption. We propose Edge-TM, an adaptive hardware/software error management policy that (i) optimistically scales the voltage beyond the edge of safe operation for better energy savings and (ii) works in combination with a hardware Transactional Memory (HTM)-based error recovery mechanism. The policy applies dynamic voltage scaling (DVS) (while keeping frequency fixed) based on the feedback provided by HTM, which makes it simple and generally applicable. Experiments on an embedded platform show our technique capable of 57% energy improvement compared to using voltage guardbands and an extra 21-24% improvement over existing state-of-the-art error tolerance solutions, at a nominal area and time overhead. © 2017 ACM.

关键词： Energy efficiency Energy conservation Energy utilization Errors hardware Reliability Semiconductor devices Storage allocation (computer) Voltage scaling Dynamic voltage scaling (DVS) Error recovery mechanisms Error tolerance hardware transactional memory Operating frequency Performance improvements Transactional memory Variability

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Interface Implementation Using Ajax for Web-Based Instruction Set Simulator

Interface Implementation Using Ajax for Web-Based Instructio...

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international conference on Advanced Information Networking and Applications Workshops (AINAW)

作者： Hideaki Yanagisawa Minoru Uehara Hideki Mori Computer Science and Electronic Engineering Tokuyama College of Technology Japan Information and Computer Sciences Toyo University Japan

SSC-DASH (Server Side C-like Design Automation Shell) has been developed as a Web-based HW/SW codesign tool for designing processors. SSC-DASH obtains a processor definition file via Web browser and generates a HW (synthesizable Verilog-HDL description) and SWDE (software Development Environment) for the generated processor. The SWDE includes ISS (Instruction Set Simulator), assembler, disassembler and compiler. For the verification of the defined processor, processor developers have to download the generated SWDE, every time, even where changes are small. To improve the usability of this system a Web-based interface for the generated SWDE is implemented using Ajax. Using Ajax, download of the SWDE becomes unnecessary and makes it possible to verify the processor on the server quickly and easily. This greatly improves the usability of the SWDE. In this paper, we describe implementation of Web-based ISS using Ajax.

关键词： hardware design languages Assembly Process design Java Programming Usability Instruction sets Computer architecture Web pages Control system synthesis

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