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international conference on Communications, Circuits and systems (ICCCAS)

作者： Qiang Wu Yunfeng Wang Jinian Bian Weimin Wu Hongxi Xue Department of Computer Science and Technology Tsinghua University Beijing China

A hierarchical CDFG model designed as an intermediate representation for hardware/software (HW/SW) codesign is presented in this paper. A new concept of transport node, which represents the communication resources of the system, is proposed in this model. Hierarchical feature can be straightly obtained through extending the definition of nodes, allowing them to nest sub-CDFG recursively. Then it is demonstrated how to build basic control constructs of branches and loops. Explaining in a short introduction to the translation process, such a hierarchical CDFG is suitable for HW/SW codesign as an intermediate representation. The hierarchical CDFG model can capture the design information from source file specified by VHDL or C language. It maintains relative simplicity while providing helpful features for HW/SW partitioning and High-level synthesis tools.

关键词： hardware Communication system control High level synthesis Wires Computer science Flow graphs Specification languages Synthesizers Control system synthesis Research and development

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Proceedings of the ninth international symposium on hardware/software codesign

Proceedings of the ninth international symposium on hardware...

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9th international Symposium on hardware/software codesign

The proceedings contains 43 papers from the conference on the Proceedings of the Ninth international Symposium on hardware/software codesign. Topic discussed include: the usage of stochastic processes in embedded system specifications;modelling and evaluation of hardware/software designs;a practical toolbox for system level communication synthesis;designing domain-specific processors;a novel parallel deadlock detection algorithm and architecture;towards effective embedded processors in codesigns: customizable partitioned caches;and development cost and size estimation starting from high-level specifications.

关键词： Embedded systems

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A flexible approach to the design of complex embedded systems

A flexible approach to the design of complex embedded system...

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Annual IEEE international ASIC/SOC conference

作者： J.M. Moya F. Moya J.C. Lopez University of Castilla La Mancha Ciudad Real Spain

Describes a new approach to hardware/software codesign for complex embedded systems, using high-level programming languages, such as C, C++, Java, or Ada. Unlike previous approaches, we do not distribute parts of the behavior between the different subsystems. We map the entire behavior onto the whole system, and the partition is made implicitly during the synthesis process. We divide the system specification into behavior, architecture and design criteria, to maximize reuse opportunities and to increase the flexibility of the design environment.

关键词： Embedded system hardware Embedded software Programming Computer languages Java Microprocessors Costs Specification languages Space technology

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Specification and synthesis of real-time embedded distributed and parallel multiprocessor-based signal processing systems

Specification and synthesis of real-time embedded distribute...

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Proceedings of the international conference on Compilers, Architecture, and synthesis for Embedded systems (CASES 2000)

作者： Janka, Randall S. Wills, Linda M. Cadence Design Systems Inc. 1117 Perimeter Center West Atlanta GA 30338 United States Sch. of Elec./Computer Engineering Georgia Institute of Technology Atlanta GA 30332-0250 United States

ISBN: (纸本)1581133383

The codesign of embedded real-time signal processing systems is complex. In certain application domains requiring high computational throughput, this complexity is due to the need to employing parallel processing and perhaps using heterogeneous processors. The use of commercial-off-the-shelf (COTS) multiprocessor (MP) hardware and software can reduce codesign complexity. Further complexity reduction can be obtained with emerging synthesis frameworks, which can generate deployable code by leveraging vendor communication and computation libraries. However, these synthesis frameworks are inadequate in providing a sound specification and design methodology (SDM) because they require the designer to first choose the implementation target before specification and design exploration. We have developed a new SDM known as MAGIC that allows the designer to capture the specification in an executable model that can then be used in design exploration to find the optimal COTS MP technology and architecture before committing to that technology. The MAGIC SDM exploits emerging open-standards based VSIPL computation middleware and MPI communication middleware to provide connectivity between specification and design with synthesis frameworks for implementation. This SDM is also shown to be applicable to the system-on-chip (SOC) domain, especially as embodied in a new framework called Virtual Component Co-design from Cadence Design systems.

关键词： Signal processing

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Coevolvable hardware platform for automatic hardware design of neural networks

Coevolvable hardware platform for automatic hardware design ...

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IEEE international conference on Industrial Technology (ICIT)

作者： O. Hammami K. Kuroda Q. Zhao K. Saito Department of Hardware University of Aizu Fukushima Japan

This paper proposes a system for the automatic hardware design of neural networks based on cooperative coevolutionary paradigms and multiple reconfigurable devices. The authors' system is composed of a logic synthesis tool, multiple reconfigurable devices and an embedded processor executing the coevolutionary algorithm. The partitioning of the engineering design process follows current practices in hardware/software codesign based on both information on arrival rate /spl lambda/ of requests and the service time /spl mu/ of the reconfigurable devices. The system is suitable under some conditions for industrial applications such as a reactive system but also because it can be connected to multiple systems in a totally networked industrial environment which allows download of the same hardware configuration on multiple on ine devices.

关键词： Neural network hardware Neural networks hardware design languages Genetic programming Network synthesis Algorithm design and analysis Approximation algorithms Logic devices Reconfigurable logic Partitioning algorithms

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hardware/software codesign for FPGA-based systems

Hardware/software codesign for FPGA-based systems

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The 1999 32nd Annual Hawaii international conference on system Sciences, HICSS-32

作者： Saul, J.M. Oxford Univ Computing Lab Oxford United Kingdom

A new codesign compiler, Dash, provides a co-synthesis and co-simulation environment for mixed FPGA/processor architectures. It compiles a C-like description to a solution containing both processors and custom hardware, and allows the descriptions of FPGA-based processors to be heavily parametrized. The user may add instructions to the processors, and the Dash software architecture allows the user to add facilities for targeting these extra instructions to the compiler. This system is being used to design a number of case studies, and a single-chip codesign of an Internet video game is used to illustrate the design flow.

关键词： Computer systems programming

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Hw/Sw codesign of embedded systems 4th

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4th international conference on Reliable software Technologies (Ada-Europe'99)

作者： Fornaciari, W Sciuto, D Politecn Milan Dipartimento Elettron & Informaz I-20133 Milan Italy

ISBN: (纸本)3540660933

The architecture of systems tailored for a specific application frequently requires cooperation among hardware and software components. The design of these systems is typically a compromise among a number of factors: cost, performance, size, development time, power consumption, etc. To cope with increasing possibilities offered by nowadays integration technology and steady demanding of shorter time-to-market, a comprehensive strategy aiming at gathering all the involved aspects of the design is becoming mandatory This new discipline, called codesign, considers in a concurrent manner all the activities involved in the design of a mixed hw/sw dedicated system: capturing of design specification and requirements, mapping of the design onto hardware and software domains, system synthesis and design verification. The paper introduces the key factors involved in the design of an embedded system, together with a description on how codesign is overcoming such problems, opening the way to a new generation of CAD frameworks supporting system-level design.

关键词： Embedded systems

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Embedded system synthesis under memory constraints

Hardware/Software Codesign - Proceedings of the Internationa...

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hardware/software codesign - Proceedings of the international Workshop 1999年 188-192页

作者： Madsen, Jan Bjorn-Jorgensen, Peter Technical Univ of Denmark Lyngby Denmark

This paper presents a genetic algorithm to solve the system synthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular interconnection structures. The synthesis is performed under memory constraints, that is, the algorithm takes into account the memory size of processors and the size of interface buffers of communication links, and in particular the complicated interplay of these. The presented algorithm is implemented as part of the LYCOS cosynthesis system.

关键词： Computer architecture

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system synthesis utilizing a layered functional model

Hardware/Software Codesign - Proceedings of the Internationa...

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hardware/software codesign - Proceedings of the international Workshop 1999年 136-140页

作者： Sander, Ingo Jantsch, Axel Royal Inst of Technology Stockholm Sweden

We propose a system synthesis method which bridges the gap between a highly abstract functional model and an efficient hardware or software implementation. The functional model is based on a formal semantics and the synchrony hypothesis. However, the use of skeletons in conjunction with a proper computational model structures the system description into three layers, the system layer, the skeleton layer, and the elementary layer. The synthesis process takes advantage of this structure and uses a different technique for each layer: (a) connection of components and processes at the system layer;(b) template based generation of compound entities possibly containing state information, memory, and complex control at the skeleton layer;this layer also determines the communication and timing behaviour;(c) direct translation into combinatorial functions at the elementary layer. Thus, without compromising the formal properties of the abstract system model we provide an efficient synthesis method.

关键词： Computer architecture

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hardware/software codesign of an avionics protocol interface system

Hardware/software codesign of an avionics protocol interface...

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IEEE international conference on Electronics, Circuits and systems (ICECS)

作者： F. Cloute J.-N. Contensou D. Esteve P. Pampagnin P. Pons Y. Favard Laboratoire d'Electronique LEN7 Enseeiht Toulouse France Aerospatiale Aèronautique Toulouse France

Design of heterogeneous hardware/software systems is not really a new idea, since designers have been used to mixing generic programmable and specific hardware components for algorithms implementation. However, with the growing systems complexity, a computer-aided codesign methodology becomes essential. A codesign methodology relies on an executable system-level specification, independent of implementation, which enables hardware/software architecture exploration and synthesis. This paper presents an application of the avionics domain: the ARINC communication protocol interface system. The codesign approach is based on the POLIS framework, coupled with the Esterel specification language.

关键词： hardware Aerospace electronics Protocols Embedded system Control systems Algorithm design and analysis Computer architecture Application software Manufacturing Digital signal processing

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