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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

共 5225 条记录，以下是101-110 订阅

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EXION: Exploiting Inter-and Intra-Iteration Output Sparsity for Diffusion Models

EXION: Exploiting Inter-and Intra-Iteration Output Sparsity ...

引用

IEEE symposium on high-performance computer architecture

作者： Jaehoon Heo Adiwena Putra Jieon Yoon Sungwoong Yune Hangyeol Lee Ji-Hoon Kim Joo-Young Kim KAIST Daejeon Republic of Korea

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Over the past few years, diffusion models have emerged as novel solutions in AI industries, offering the capability to generate diverse, multi-modal outputs such as images, videos, and motions from input prompts (i.e., text). Despite their impressive capabilities, diffusion models face significant challenges in computing, including excessive latency and energy consumption due to the numerous iterations in model architecture. Although prior works specialized in transformer acceleration can be applied to diffusion models, given that transformers are key components, the problem of the iterative nature of diffusion models still needs to be *** this paper, we present EXION, the first software-hardware co-designed diffusion accelerator that solves the computation challenges of excessive iterations by exploiting the unique inter-and intra-iteration output sparsity in diffusion models. To this end, we propose two software-level optimizations in EXION. First, we introduce the FFN-Reuse algorithm that identifies and skips redundant computations in FFN layers across different iterations (i.e., inter-iteration sparsity). Second, we use a modified eager prediction method that employs two-step leading-one detection to accurately predict the attention score in diffusion models, skipping unnecessary computations within an iteration (i.e., intra-iteration sparsity). We also introduce a novel data compaction mechanism named ConMerge, which can enhance hardware utilization by condensing and merging large and sparse matrices into small and compact forms. Finally, EXION has a dedicated hardware architecture that supports the above sparsity-inducing algorithms, translating high output sparsity into improved energy efficiency and performance. To verify the feasibility of the EXION accelerator, we first demonstrate that it has no impact on accuracy in various types of multi-modal diffusion models, including text-to-motion, -audio, -image, and -video. We then instantiate EXION in b

关键词： Graphics processing units computer architecture Prediction methods Diffusion models Transformers Prediction algorithms Energy efficiency Sparse matrices Servers Optimization

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EIGEN: Enabling Efficient 3DIC Interconnect with Heterogeneous Dual-Layer Network-on-Active-Interposer

EIGEN: Enabling Efficient 3DIC Interconnect with Heterogeneo...

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IEEE symposium on high-performance computer architecture

作者： Siyao Jia Bo Jiao Haozhe Zhu Chixiao Chen Qi Liu Ming Liu State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Chiplet-based 3DICs have emerged as modular solutions for large-scale, high-performance computing systems. However, unlike monolithic Network-on-Chips (NoCs), 3DICs using active interposers encounter difficulties in managing heterogeneous and high-load network traffic patterns. The emerging field of Networks-on-Active-Interposer (NOAI), independently designed from top dies’ interconnects, is desired to address these challenges by supporting flexible topologies, low-latency memory access, and reduced traffic congestion. To satisfy the requirements, we propose a heterogeneous dual-layer interconnect architecture, EIGEN, for chiplet-interposer systems, along with a reinforcement learning (RL)-based routing framework, which can provide efficient and flexible communication for chiplet-based 3DICs. EIGEN features an application-aware switch-programable interconnection layer (AspLayer) and a dynamic packet-routing interconnection layer (DynLayer) on the interposer, respectively. To optimize inter-chiplet data communication, we also develop an RL-based path routing framework tailored to this dual-layer architecture. The RL framework’s state space includes topology, network, and memory metrics, while the RL reward is set as the product of average packet latency and link utilization. The effectiveness of EIGEN is demonstrated through different applications where CPU, GPU, and AI accelerator chiplets are integrated via NOAI. Simulation results show that the proposed EIGEN achieves up to $\mathbf{6 7. 1 6 \%}$ latency reduction, $\mathbf{5 3. 8 9 \%}$ hops reduction and $\mathbf{1 1. 2 1 \%}$ runtime reduction compared to the state-of-the-art (SOTA) chiplets interconnect architectures. Furthermore, sensitivity analysis of network scaling shows that the EIGEN architecture and framework exhibit strong scalability, with latency reduction of $\mathbf{2 0. 9 6 \%}$ to $\mathbf{5 2. 7 7 \%}$ and hop reduction of $\mathbf{1 9. 7 2 \%}$ to $\mathbf{4 3. 4 1 \%}$ as the system scales fr

关键词： Runtime Network topology Chiplets Integrated circuit interconnections computer architecture Reinforcement learning Routing Topology Low latency communication Traffic congestion

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PROCA: Programmable Probabilistic Processing Unit architecture with Accept/Reject Prediction & Multicore Pipelining for Causal Inference

PROCA: Programmable Probabilistic Processing Unit Architectu...

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IEEE symposium on high-performance computer architecture

作者： Yihan Fu Anjunyi Fan Wenshuo Yue Hongxiao Zhao Daijing Shi Qiuping Wu Jiayi Li Xiangyu Zhang Yaoyu Tao Yuchao Yang Bonan Yan Institute for Artificial Intelligence Peking University Beijing China Beijing Advanced Innovation Center for Integrated Circuits School of Integrated Circuits Peking University Beijing China Independent Researcher School of Electronic and Computer Engineering Peking University Shenzhen China Chinese Institute for Brain Research Beijing China

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Causal inference is an important field in data science and cognitive artificial intelligence. It requires the construction of complex probabilistic models to describe the causal relationships between random variables. Probabilistic models rely on probabilistic programming as a flexible framework. However, the computing speed of probabilistic programming is often hindered by the extensive use of Markov chain Monte Carlo (MCMC) algorithms, even though they are powerful in Bayesian inference. To accelerate MCMC, this work presents PROCA, a programmable MCMC-based probabilistic processing unit architecture. PROCA exploits processing-in-memory function units to generate new samples of Markov chains. PROCA is programmable to execute the computation for arbitrary forms of posterior distribution formulas that software probabilistic programming frameworks support. We develop a novel accept/reject prediction methodology to accelerate the sequential MCMC computation, thereby introducing efficient multi-core pipelining methods. We implement and validate the PROCA architecture with commercial process development kits. The implementation is evaluated based on 9 representative benchmarks, covering PyMC official tutorial probabilistic problems, single-variable probabilistic problems, and real-world causal inference problems. Our comprehensive experiments demonstrate that PROCA achieves a speedup of 172~4871 $\times$ compared to Intel Xeon Gold CPU, $42 \sim 1058 \times$ compared to NVIDIA A100 GPU, and $1.765 \times$ over state-of-the-art MCMC accelerators, respectively. PROCA achieves comparable statistical robustness to the software probabilistic programming frameworks. Compared with state-of-the-art MCMC domain-specific accelerators, our design boosts the energy efficiency by $9.47 \times$.

关键词： Computational modeling Software algorithms Graphics processing units computer architecture Tutorials Programming Probabilistic logic Software Computational efficiency Pipeline processing

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Efficient and Distributed Computation of Electron Repulsion Integrals on AMD AI Engines

Efficient and Distributed Computation of Electron Repulsion ...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Johannes Menzel Christian Plessl Department of Computer Science Paderborn Center for Parallel Computing Paderborn University Paderborn Germany

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

computing electron repulsion integrals (ERIs) is the major computational bottleneck of many quantum mechanical simulation methods, requiring trillions of ERI evaluations per time step. While the computation of independent ERIs is embarrassingly parallel, the efficient computation of individual ERIs on modern processor cores is difficult due to both an insufficient cache size for intermediates of the computation and irregular memory access patterns that are difficult to vectorize. In this paper, we present how our implementation on the AI Engine (AIE) architecture addresses both of these problems. First, we have defined a flexible graph structure, which we call an ERI-Engine, that can be implemented for all 231 canonical ERI quartets from {ss|ss} to {hh| hh} by distributing the computation over 2–14 AIEs. Second, for the larger quartets, we have devised a novel vectorization scheme that leverages the advanced floating-point unit of the AIEs, while also supporting vectorization of independent ERIs for the smaller quartets. Finally, ERI-Engines are horizontally and vertically stackable to fill the entire AIE array, and in particular, the vertically stacked ERI-Engines form a column that uses one or more time-shared channels to stream the results out of the AIE array, almost completely hiding the computational phases of individual ERI-Engines. In terms of absolute performance, we are competitive with recent high-performance implementations of ERI algorithms on FPGAs (SERI) and GPUs (LibintX), as well as well-established highly optimized CPU libraries (Libint, Libcint), while being the unequivocal leader in terms of energy efficiency.

关键词： Phased arrays Quantum computing Memory management Quantum mechanics Libraries Computational efficiency Artificial intelligence Engines Field programmable gate arrays Electrons

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Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM

Make LLM Inference Affordable to Everyone: Augmenting GPU Me...

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IEEE symposium on high-performance computer architecture

作者： Lian Liu Shixin Zhao Bing Li Haimeng Ren Zhaohui Xu Mengdi Wang Xiaowei Li Yinhe Han Ying Wang Chinese Academic of Sciences Institute of Computing Technology University of Chinese Academy of Sciences Zhongguancun Laboratory Chinese Academy of Sciences Institute of Microelectronics School of Information Science and Technology ShanghaiTech University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

The billion-scale Large Language Models (LLMs) necessitate deployment on expensive server-grade GPUs with large-storage HBMs and abundant computation capability. As LLM-assisted services become popular, achieving cost-effective LLM inference on budget-friendly hardware becomes the current trend. This has sparked extensive research into relocating LLM parameters from expensive GPUs to external host memory. However, the restricted bandwidth between the host and GPU memory limits the inference performance of existing solutions. This work introduces Hermes, a budget-friendly system that leverages the near-data processing units (NDP) within commodity DRAM DIMMs to enhance the performance of a single consumer-grade GPU, achieving efficient LLM inference. We recognize that the inherent activation sparsity in LLMs naturally divides weight parameters into two categories, termed “hot” and “cold” neurons, respectively. Hot neurons, which consist of only approximately 20% of all weight parameters, account for 80% of the total computational load. In contrast, cold neurons make up the other 80% of parameters but are responsible for just 20% of the computational workload. Leveraging this observation, we propose a heterogeneous computing strategy: mapping hot neurons to a single computation-efficient GPU without large-capacity HBMs, while offloading cold neurons to NDP-DIMMs, which offer large memory size but limited computation capabilities. In addition, the dynamic nature of activation sparsity necessitates a real-time partition of hot and cold neurons and adaptive remapping of cold neurons across multiple NDP-DIMM modules. To tackle these issues, we introduce a lightweight predictor that ensures optimal real-time neuron partition and adjustment between GPU and NDP-DIMMs. Furthermore, we utilize a window-based online scheduling mechanism to maintain load balance among multiple NDP-DIMM modules. In summary, Hermes facilitates the deployment of LLaMA2-70B on consumer-grade hardware

关键词： Processor scheduling Large language models Neurons Graphics processing units Random access memory computer architecture Market research Real-time systems Hardware Heterogeneous networks

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Ternary-Valued Associative Processor Design

Ternary-Valued Associative Processor Design

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IEEE international symposium on Quality Electronic Design

作者： Mira Hout Rouwaida Kanj Ahmed M. Eltawil Mohammed E. Fouda ECE Dept. American University of Beirut Lebanon Synopsys Inc Austin TX USA King Abdullah University of Science and Technology (KAUST) Thuwal Saudi Arabia Rain Neuromorphics Inc. San Francisco CA USA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

In-memory computing architectures have emerged as a promising solution to address the memory-wall bottleneck and enable efficient vectorized and parallel arithmetic operations. This paper proposes a hardware architecture and algorithms for ternary-valued associative processors (TAP) which is a critical step toward broadening their computational versatility. To facilitate the in-memory implementation of complex arithmetic and logic functions, we introduce an efficient methodology for the automatic generation of corresponding look-up tables (LUTs). A SPICE-MATLAB co-simulator is developed to evaluate the performance of the proposed TAP-based in-memory ternary adder in terms of energy consumption, computational delay, and area overhead. Comparative analysis demonstrates that the ternary AP adder achieves energy and area reductions of 11% and 6.2%, respectively, compared to its binary counterpart. Furthermore, compared to state-of-the-art ternary carry-lookahead adder, the proposed solution exhibits around 100x and 9.5x reduction in energy and delay, respectively. This work highlights the potential of in-memory and parallel computing processors to high-efficiency arithmetic operations, offering scalable and energy-efficient solutions for emerging computational workloads.

关键词： Energy consumption Program processors computer architecture Parallel processing In-memory computing Energy efficiency Delays Table lookup Adders Arithmetic

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A FeFET-Based Compute-in-Memory architecture on FPGA for Neural Network Inference

A FeFET-Based Compute-in-Memory Architecture on FPGA for Neu...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Minghan Jiang Yonggen Li Rui Xiao Haibin Shen Kejie Huang Zhejiang University China

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Implementing compute-in-memory (CIM) architectures on FPGA offers an effective solution to the von Neumann bottleneck by enabling fast configuration and computation directly within memory. Traditional custom solutions rely on the modification of block RAM (BRAM) to implement memory computing. However, single-word-line activation of BRAM results in low parallelism, and the need for additional adder trees to accumulate partial sums further limits efficiency. To overcome these limitations, we propose a CIM core based on a 2T1C structure as a replacement for BRAM units. This core utilizes a charge redistribution mechanism and reuse of ADC capacitors, achieving high parallelism, low power consumption, and a compact area. By incorporating computational capabilities within a single cell, our design enables dual parallelism, further enhancing performance and efficiency. In addition, we present an automated deployment and mapping tool for deep neural networks (DNNs) on FPGA, allowing users to rapidly develop FPGA-based solutions for different network architectures. Compared to state-of-the-art solutions, our design achieves a peak throughput improvement of 4.5× and a reduction in area by 53%.

关键词： Power demand Random access memory computer architecture Parallel processing In-memory computing Throughput Common Information Model (computing) Computational efficiency Registers Field programmable gate arrays

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Predicting DRAM-Caused Risky VMs in Large-Scale Clouds

Predicting DRAM-Caused Risky VMs in Large-Scale Clouds

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IEEE symposium on high-performance computer architecture

作者： Yaoguang Yong Xiaoming Du Xuhua Ma Yuxiang Wang Bin Yao Xudong Zheng Huite Yi Shanghai Jiao Tong University Alibaba Cloud

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

DRAM failures are one of the leading failures in large-scale clouds. Previous studies focus on predicting DRAM uncorrectable errors (UEs) and mitigating the impact of DRAM failures through node-level workload migration and proactive dual in-line memory module (DIMM) replacement. For cloud systems, node migration means migrating all virtual machines (VMs) to other nodes. Such a coarse-grained migration consumes considerable resources. Inspired by the observation that DRAM errors tend to cluster in space, this paper proposes Pegasus, the first VM-level solution to mitigate DRAM failures. The key idea of Pegasus is to use the VM as the basic unit for predicting DRAM failures instead of the whole node. Specifically, we introduce a new concept of DRAM-caused risky VMs, which causes node unavailability when accessed. We design a novel Error-VM mapping framework deployed on a large-scale cloud. Statistical results confirm that DRAM errors are concentrated in the address space managed by a small number of VMs. By combining ECC and spatio-temporal features, our predictor achieves decent performance. Pegasus has been deployed online on over $\mathbf{3 0 0, 0 0 0}$ nodes in the production cloud. The comparative study shows that the prediction performance of Pegasus is comparable to node-level solutions. Meanwhile, our approach offers over $\mathbf{7 0 \%}$ lower costs and avoids more than $\mathbf{1 0 \%}$ of VM crashes compared to node-level mitigation.

关键词： Cloud computing Costs Prevention and mitigation Random access memory Production Memory modules Virtual machines computer crashes Error correction codes Engines

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Lincoln: Real-Time 50~100B LLM Inference on Consumer Devices with LPDDR-Interfaced, Compute-Enabled Flash Memory

Lincoln: Real-Time 50~100B LLM Inference on Consumer Devices...

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IEEE symposium on high-performance computer architecture

作者： Weiyi Sun Mingyu Gao Zhaoshi Li Aoyang Zhang Iris Ying Chou Jianfeng Zhu Shaojun Wei Leibo Liu School of Integrated Circuits Tsinghua University Beijing National Research Center for Information Science and Technology (BNRist) Beijing China Institute for Interdisciplinary Information Sciences Tsinghua University Shanghai Qi Zhi Institute Shanghai China MetaX Technology Beijing China

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

With the widespread use of large language models (LLMs), and with the privacy and cost concerns on cloud-based services, vendors are now pushing LLM inference to consumer devices. However, current attempts only enable real-time inference of low-quality small-sized LLMs. Large-sized LLMs have to load most of their weights from Flash storage for every execution iteration, which dominates the execution time of both the prefill and the generation phase. This performance bottleneck is attributed to both the low internal Flash memory bandwidth and the low transmission bandwidth between Flash and the Neural Processing Unit (NPU). To tackle these two challenges, we present Lincoln, a device-architecture co-design solution with LPDDR-interfaced, Compute-Enabled Flash Memory. On the device level, we boost the Flash internal bandwidth by improving upon existing array shrinking methods, to enable lower read latency and more parallel Flash planes within each Flash die. We specifically leverage 3D hybrid bonding, which is already adopted in consumer Flash products, to maintain high area efficiency and low density loss. On the architecture level, to leverage such increased internal bandwidth for resolving the transmission bottleneck, we propose two solutions for the two distinct phases of LLMs. For the compute-intensive prefill phase, we let Flash devices use the existing high-speed LPDDR interface (originally for DRAM), which offers much higher transmission bandwidth to the NPU than the conventional Flash interface, while maintaining good cost and area efficiency. For the memory-intensive generation phase, we rely on hybrid-bonding-based near-Flash computing to fully utilize the internal Flash bandwidth, and further equip with speculative decoding to eventually reach the real-time latency goal. Our evaluation shows that Lincoln enables real-time inference, with up to $13.23 \times$ and $254.1 \times$ speedups for LLM prefill and generation phases over conventional SSD-based syste

关键词： performance evaluation Privacy Costs Three-dimensional displays Large language models Random access memory Bandwidth computer architecture Real-time systems Flash memories

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To Cross, or Not to Cross Pages for Prefetching?

To Cross, or Not to Cross Pages for Prefetching?

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IEEE symposium on high-performance computer architecture

作者： Georgios Vavouliotis Marti Torrents Boris Grot Kleovoulos Kalaitzidis Leeor Peled Marc Casas Computing Systems Lab Huawei Zurich Research Center Barcelona Supercomputing Center University of Edinburgh Boole Lab Huawei Tel-Aviv Research Center Universitat Politecnica de Catalunya

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Despite processor vendors reporting that cache prefetchers operating with virtual addresses are permitted to cross page boundaries, academia is focused on optimizing cache prefetching for patterns within page boundaries. This work reveals that page-cross prefetching at the first-level data cache (L1D) is seldom beneficial across different execution phases and workloads while showing that state-of-the-art L1D prefetchers are not very accurate at prefetching across page boundaries. In response, we propose $M O K A$, a holistic framework for designing Page-Cross Filters, i.e., microarchitectural schemes that ensure effective and accurate prefetching across page boundaries. MOKA combines (i) hashed perceptron predictors that use prefetcher-independent program features, (ii) predictors that adapt decisions based on the system state (e.g., TLB pressure), and (iii) a scheme to dynamically optimize predictions across different execution phases and workload types. We use the MOKA framework to prototype a Page-Cross Filter, named DRIPPER, for three relevant L1D prefetchers (Berti [60], IPCP [61], BOP [57]). We show that DRIPPER accurately enables pagecross prefetching only when it is beneficial for performance. For instance, Berti [60] (state-of-the-art prefetcher) combined with DRIPPER improves single-core geomean performance over Berti that always permits page-cross prefetches and Berti that always discards page-cross prefetches by $\mathbf{1 . 7 \%}(\mathbf{1 . 2 \%})$ and $\mathbf{2 . 5 \%}(\mathbf{2 . 1 \%})$ across 218 seen (178 unseen) workloads, respectively. Across 300 8 -core mixes, the corresponding geomean speedups are $2.0 \%$ and $3.3 \%$. Finally, we show that DRIPPER provides consistent benefits when both 4KB pages and 2MB large pages are used.

关键词： Filters Accuracy Microarchitecture Prefetching Prototypes computer architecture

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