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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

共 5212 条记录，以下是121-130 订阅

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Comparing performance of C compilers optimizations on different multicore architectures 29

Comparing performance of C compilers optimizations on differ...

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8th international symposium on computer architecture and high performance computing (SBAC-PADW)

作者： Machado, Roger S. Almeida, Ricardo B. Jardim, Andre D. Pernas, Ana M. Yamin, Adenauer C. Cavalheiro, Gerson Geraldo H. Univ Fed Pelotas PPGC 1 Gomes Carneiro St Pelotas RS Brazil

ISBN: (纸本)9781538648193

Multithread programming tools become popular for exploitation of high performance processing with the dissemination of multicore processors. In this context, it is also popular to exploit compiler optimization to improve the performance at execution time. In this work, we evaluate the performance achieved by the use of flags -O1, -O2, and -O3 of two C compilers (GCC and ICC) associated with five different APIs: Pthreads, C++11, OpenMP, Cilk Plus, and TBB. The experiments were performed on two distinct but compatible architectures (Intel Xeon and AMD Opteron). In our experiments, the use of optimization improves the performance independently from the API. We observe that the application scheduling performed by the programming interfaces providing an application level scheduler has more impact on the final performance than the optimizations.

关键词： Optimization Program processors Programming Benchmark testing computer architecture Tools Standards

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Towards Optimizing Computational Costs of Federated Learning in Clouds 33

Towards Optimizing Computational Costs of Federated Learning...

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33rd IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Brum, Rafaela Drummond, Lucia Castro, Maria Clicia Teodoro, George Fluminense Fed Univ Niteroi RJ Brazil Univ Estado Rio De Janeiro Rio De Janeiro Brazil Univ Fed Minas Gerais Belo Horizonte MG Brazil

ISBN: (纸本)9781665417303

Federated Learning is a strategy where distributed training datasets are processed by several clients coordinated by a central server that keeps the global learning model. This approach is very attractive in the biomedical domain because it allows the use of private datasets from multiple institutions to train a model without the need of sharing the data. Moreover, Machine Learning approaches often require larger training samples than what can be afforded by a single institution. In this work, we are interested in analyzing the performance of a Tumor-Infiltrating Lymphocytes Classification problem when solved by a federated learning approach deployed in a commercial cloud. In the presented evaluation, we consider executions of a federated learning implementation on accelerated instance types of the AWS EC2, on on-demand and spot markets, while varying the number of clients. The obtained results showed the improvement of the accuracy and execution times when the number of clients increases. They also revealed that, although the spot instances suffered from revocations, their use could significantly reduce the financial costs compared to the on-demand one.

关键词： Cloud computing Federated Learning GPU instances

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Efficient In-Situ Quantum computing Simulation of Shor's and Grover's Algorithms 29

Efficient In-Situ Quantum Computing Simulation of Shor's and...

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8th international symposium on computer architecture and high performance computing (SBAC-PADW)

作者： Avila, Anderson Reiser, Renata H. S. Yamin, Adenauer C. Pilla, Mauricio L. Univ Fed Pelotas Ctr Technol Dev 1st Gomes Carneiro St Pelotas Brazil

ISBN: (纸本)9781538648193

Exponential increase and global access to read/write memory states in quantum computing simulation limit both the number of qubits and quantum transformations that can be currently simulated. Although quantum computing simulation is parallel by nature, spatial and temporal complexity are major performance hazards, making this an important application for HPC. A new methodology employing reduction and decomposition optimizations has shown great results, but its GPU implementation could be further improved. In this work, we intend to do a new implementation for in-situ GPU simulation that better explores its resources without requiring further HPC hardware. Shor's and Grover's algorithms are simulated and compared to the previous version and to LIQUi vertical bar >'s simulator, showing better results with relative speedups up to 15.5x and 765.76x respectively.

关键词： Quantum computing Computational modeling Integrated circuit modeling Optimization Graphics processing units Tensile stress Complexity theory

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CLAP-Bot: a framework for automatic optimization of high-performance elastic applications on the Clouds 33

CLAP-<i>Bot</i>: a framework for automatic optimization of h...

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33rd IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Napoli, Otavio Oliveira Pinton, Gustavo Ciotto Borin, Edson Univ Estadual Campinas Inst Comp Campinas Brazil

ISBN: (纸本)9781665417303

The computational cloud has become notorious due to its business model, where the user only pays to use the system, with no acquisition or maintenance costs. However, cloud providers such as AWS EC2 and Google computing Engine offer several virtual machine types making it difficult to choose which of them is most suitable to the user's application and objective. In this work, we present CLAP-Bot, a system that automatically monitors and adjusts the computing infrastructure based on some recipe. CLAP-But is built over CLAP, allowing creating and managing computational clusters in different cloud providers. The recipe is a component that can read application metrics and execute a set of actions on the infrastructure. The application monitor is decoupled from the recipe, allowing it to be used transparently with different applications. We show how CLAP-Bot works by implementing three dynamic provisioning policies as recipes and evaluating them. Besides that, together with CLAP-Bot we also present CLAP-Bot-Sim, a discrete event simulator that allows modeling the use of a given recipe without the need to instantiate any virtual machine. CLAP-Bot-Sim also allows modeling dynamic events, such as virtual machine interruptions and instance price oscillation over lime. We show that CLAP-Bot-Sim can accurately simulate the effects of recipes on the computing infrastructure and can easily be interchanged with CLAP-Bot.

关键词： Dynamic optimization system Cloud computing Cluster management Simulator

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Efficient Pathfinding Co-processors for FPGAs 29

Efficient Pathfinding Co-processors for FPGAs

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8th international symposium on computer architecture and high performance computing (SBAC-PADW)

作者： Nery, Alexandre S. Sena, Alexandre C. Guedes, Leandro S. Univ Estado Rio De Janeiro IME Dept Informat & Ciencia Computacao Rio De Janeiro Brazil Inst Fed Educ Ciencia & Tecnol Mato Grosso do Sul Dept Informat Corumba Brazil

ISBN: (纸本)9781538648193

Pathfinding algorithms are at the heart of several classes of applications, such as network appliances (routing), GPS navigation and autonomous cars, which are related to recent trends in Artificial Intelligence and Internet of Things (IoT). Moreover, advances in semiconductor miniaturization technologies have enabled the design of efficient Systems-on-Chip (SoC) devices, with demanding performance requirements and energy consumption constraints. Such systems might include Field Programmable Gate Arrays (FPGAs) to allow the design of customized co-processors that yield lower power consumption and higher performance. Therefore, this work aims at designing and evaluating four efficient pathfinding co-processors, each one implementing a different well-known pathfinding algorithm: breadth-first, dijkstra, greedy and a-star. Each co-processor is designed using Xilinx high-Level Synthesis (HLS) compiler and is implemented in the programming logic of a Xilinx FPGA embedded with an ARM microprocessor, which is in charge of controlling the set of co-processors. Extensive performance, circuit-area and energy consumption results shows that each co-processor can efficiently execute a pathfinding algorithm, paving the way for novel dedicated accelerators.

关键词： Field programmable gate arrays Protocols computer architecture Algorithm design and analysis Random access memory Ports (computers) Logic arrays

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Efficient virtual channel organization and congestion avoidance in multicore NoC systems 26

Efficient virtual channel organization and congestion avoida...

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26th IEEE international symposium on computer architecture and high performance computing workshops, SBAC-PADW 2014

作者： Oveis-Gharan, Masoud Khan, Gul N. Electrical and Computer Engineering Ryerson University 350 Victoria St TorontoONM5B 2K3 Canada

ISBN: (纸本)9781479970148

Dynamically Allocated Multi Queues (DAMQ) is an effective mechanism to achieve Virtual Channel (VC) based flow control with maximum buffer utilization in multi-core Network-on-Chip (NoC) systems. We present a new methodology to remedy some of the drawbacks of DAMQ technique. The architectural design of a DAMQ router inputport that uses minimal hardware is introduced. Our input-port design saves 70% of combinational-logic and 14.7% register hardware as compared to conventional Link-List input-port. We also present an efficient mechanism to remove traffic congestion in on-chip communication for NoC systems. It improves latency and throughput by 30% and 23% respectively as compared to conventional dynamic Virtual Channel design. © 2014 IEEE.

关键词： Traffic congestion

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An Instruction-Set Extension to Support Approximate Multicore Processors

An Instruction-Set Extension to Support Approximate Multicor...

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2024 international symposium on computer architecture and high performance computing workshops

作者： Catelan, Daniela Sovernigo, Felipe Duenha, Liana Santos, Ricardo Fed Univ Mato Grosso Sul UFMS Coll Comp FACOM Campo Grande MS Brazil

ISBN: (纸本)9798331506742;9798331506735

Approximate computing encompasses several techniques that can be applied from the application level to the circuit level, offering better performance and lower power consumption at the cost of a lack of precision. Multicore architectures, by distributing the workload among several processing cores, can meet the demand for performance while remaining within the energy limitations. This work focuses on the usage of heterogeneous multicore designs, comprised of approximate cores. Specifically, this paper proposes an extension to RISC-V Instruction-Set architecture (ISA) that supports approximate operations. We have designed a sub-set of approximate integer and floating point instructions that, in turn, are embedded in the operations of mathematical functions (sine, cosine, tangent, exponential, and logarithmic). The proposed technique is named Instruction-Level Approximate Functions (ILAF) and it has been evaluated on accuracy, number of instructions, cycles, and power in six applications using the ACCEPT compiler framework and the SPIKE RISC-V simulator. We have performed experiments comparing our approach to non-approximate and approximate versions of each application. The results show significant improvements, such as a 94.18% reduction in power consumption in the CUBIC application and 78.39% cycles reduction in the IDENTITY LOG2 application. Additionally, a detailed and comprehensive analysis of ILAF and a software-based approximate technique (FastApprox) in the BLACKSCHOLE application showed that ILAF achieved a reduction in power consumption of 3.02x with 19% code coverage.

关键词： approximate computing multicore heterogeneous processors approximate instructions ILAF

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Offloading the Training of an I/O Access Pattern Detector to the Cloud 33

Offloading the Training of an I/O Access Pattern Detector to...

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33rd IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Kunas, Cristiano A. Serpa, Matheus S. Bez, Jean Luca Padoin, Edson L. Navaux, Philippe O. A. Fed Univ Rio Grande do Sul UFRGS Inst Informat Porto Alegre RS Brazil Reg Univ Northwestern Rio Grande do Sul UNIJUI Ijui Brazil Lawrence Berkeley Natl Lab Berkeley CA USA

ISBN: (纸本)9781665417303

I/O operations are a bottleneck for numerous applications, so optimizing the performance of these operations is of paramount importance. Many techniques explore and apply optimizations to different layers of the I/O stack to improve performance. The difficulty that arises is that the workload changes constantly. So detecting access patterns correctly, at run-time, becomes essential for systems that seek to self-adjust their parameters. Furthermore, the I/O pattern detection techniques should represent minimal overhead and should be able to perform detection as quickly as possible. This paper approaches a machine learning technique for detecting the I/O access patterns and proposes offloading the local training workload to the cloud using a TPU accelerator. Such an approach does not interfere with classifier accuracy (reaching up to 99% accuracy). Still, it allows the training to be asynchronous, enabling the local machine to allocate its computing resources to scientific applications while the model is trained or updated in the cloud.

关键词： high-performance computing access pattern detection classification TPU cloud

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Towards a Dataflow Runtime Environment for Edge, Fog and In-Situ computing 29

Towards a Dataflow Runtime Environment for Edge, Fog and In-...

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8th international symposium on computer architecture and high performance computing (SBAC-PADW)

作者： Carvalho, Caio B. G. Ferreira, Victor C. Franca, Felipe M. G. Bentes, Cristiana Alves, Tiago A. O. Sena, Alexandre C. Marzulo, Leandro A. J. PESC COPPE UFRJ Rio De Janeiro Brazil DESC FEN UERJ Rio De Janeiro Brazil DICC IME UERJ Rio De Janeiro Brazil

ISBN: (纸本)9781538648193

In the dataflow computation model, instructions or tasks are fired according to their data dependencies, instead of following program order, thus allowing natural parallelism exploitation. Dataflow has been used, in different flavors and abstraction levels (from processors to runtime libraries), as an interesting alternative for harnessing the potential of modern computing systems. Sucuri is a dataflow library for Python that allows users to specify their application as a dependency graph and execute it transparently at clusters of multicores, while taking care of scheduling issues. Recent trends in Fog and In-situ computing assumes that storage and network devices will be equipped with processing elements that usually have lower power consumption and performance. An important decision on such system is whether to move data to traditional processors (paying the communication costs), or performing computation where data is sitting, using a potentially slower processor. Hence, runtime environments that deal with that trade-off are extremely necessary. This work takes a first step towards a solution that considers Edge/Fog/In-situ in a dataflow runtime. We use Sucuri to manage the execution in a small system with a regular PC and a Parallella board. Experiments with text processing applications running with different input sizes, network latency and packet loss rates allow a discussion of scenarios where this approach would be fruitful.

关键词： Program processors Libraries computer architecture Runtime environment performance evaluation Field programmable gate arrays

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high-level dataflow programming for reconfigurable computing 26

High-level dataflow programming for reconfigurable computing

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26th IEEE international symposium on computer architecture and high performance computing workshops, SBAC-PADW 2014

作者： Sérot, J. Berry, F. Institut Pascal Université Blaise Pascal / CNRS Clermont-Ferrand France

ISBN: (纸本)9781479970148

In many application domains, FPGAS are now promoted as a way of getting round the restrictions of specific CPU designs on system scalability. However, in the current state-of-the art, programming FPGAS remains essentially a hardware-oriented activity, relying on dedicated hardware description languages such as VHDL or Verilog. Using these languages requires expertise in digital design and in practice this limits the applicability of FPGA-based solutions. This is particulary true for stream-processing applications, in which some processing must be carried out "on the fly" on digital data streams. In this context, the dataflow programming model offers a very effective way to reduce the gap between high-level formulations and low-level implementations. To support this claim, the authors have recently introduced CAPH, a domain specific language, offering a fully-automated compilation path from high-level dataflow descriptions to FPGA configuration for stream-processing applications. This paper is a introduction to the CAPH language, giving its motivations and main design principles and exposing the basic features of its syntax, semantics and compilation. It also points to experimental results showing that, at least for stream-processing applications, the dataflow model of computation, used jointly as a programming model and an execution model, can offer a very effective way to conciliate abstraction and efficiency when programming FPGAS. © 2014 IEEE.

关键词： computer hardware description languages

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