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2024 international symposium on computer architecture and high performance computing workshops

作者： Catelan, Daniela Sovernigo, Felipe Duenha, Liana Santos, Ricardo Fed Univ Mato Grosso Sul UFMS Coll Comp FACOM Campo Grande MS Brazil

ISBN: (纸本)9798331506742;9798331506735

Approximate computing encompasses several techniques that can be applied from the application level to the circuit level, offering better performance and lower power consumption at the cost of a lack of precision. Multicore architectures, by distributing the workload among several processing cores, can meet the demand for performance while remaining within the energy limitations. This work focuses on the usage of heterogeneous multicore designs, comprised of approximate cores. Specifically, this paper proposes an extension to RISC-V Instruction-Set architecture (ISA) that supports approximate operations. We have designed a sub-set of approximate integer and floating point instructions that, in turn, are embedded in the operations of mathematical functions (sine, cosine, tangent, exponential, and logarithmic). The proposed technique is named Instruction-Level Approximate Functions (ILAF) and it has been evaluated on accuracy, number of instructions, cycles, and power in six applications using the ACCEPT compiler framework and the SPIKE RISC-V simulator. We have performed experiments comparing our approach to non-approximate and approximate versions of each application. The results show significant improvements, such as a 94.18% reduction in power consumption in the CUBIC application and 78.39% cycles reduction in the IDENTITY LOG2 application. Additionally, a detailed and comprehensive analysis of ILAF and a software-based approximate technique (FastApprox) in the BLACKSCHOLE application showed that ILAF achieved a reduction in power consumption of 3.02x with 19% code coverage.

关键词： approximate computing multicore heterogeneous processors approximate instructions ILAF

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Offloading the Training of an I/O Access Pattern Detector to the Cloud 33

Offloading the Training of an I/O Access Pattern Detector to...

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33rd IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Kunas, Cristiano A. Serpa, Matheus S. Bez, Jean Luca Padoin, Edson L. Navaux, Philippe O. A. Fed Univ Rio Grande do Sul UFRGS Inst Informat Porto Alegre RS Brazil Reg Univ Northwestern Rio Grande do Sul UNIJUI Ijui Brazil Lawrence Berkeley Natl Lab Berkeley CA USA

ISBN: (纸本)9781665417303

I/O operations are a bottleneck for numerous applications, so optimizing the performance of these operations is of paramount importance. Many techniques explore and apply optimizations to different layers of the I/O stack to improve performance. The difficulty that arises is that the workload changes constantly. So detecting access patterns correctly, at run-time, becomes essential for systems that seek to self-adjust their parameters. Furthermore, the I/O pattern detection techniques should represent minimal overhead and should be able to perform detection as quickly as possible. This paper approaches a machine learning technique for detecting the I/O access patterns and proposes offloading the local training workload to the cloud using a TPU accelerator. Such an approach does not interfere with classifier accuracy (reaching up to 99% accuracy). Still, it allows the training to be asynchronous, enabling the local machine to allocate its computing resources to scientific applications while the model is trained or updated in the cloud.

关键词： high-performance computing access pattern detection classification TPU cloud

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Towards a Dataflow Runtime Environment for Edge, Fog and In-Situ computing 29

Towards a Dataflow Runtime Environment for Edge, Fog and In-...

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8th international symposium on computer architecture and high performance computing (SBAC-PADW)

作者： Carvalho, Caio B. G. Ferreira, Victor C. Franca, Felipe M. G. Bentes, Cristiana Alves, Tiago A. O. Sena, Alexandre C. Marzulo, Leandro A. J. PESC COPPE UFRJ Rio De Janeiro Brazil DESC FEN UERJ Rio De Janeiro Brazil DICC IME UERJ Rio De Janeiro Brazil

ISBN: (纸本)9781538648193

In the dataflow computation model, instructions or tasks are fired according to their data dependencies, instead of following program order, thus allowing natural parallelism exploitation. Dataflow has been used, in different flavors and abstraction levels (from processors to runtime libraries), as an interesting alternative for harnessing the potential of modern computing systems. Sucuri is a dataflow library for Python that allows users to specify their application as a dependency graph and execute it transparently at clusters of multicores, while taking care of scheduling issues. Recent trends in Fog and In-situ computing assumes that storage and network devices will be equipped with processing elements that usually have lower power consumption and performance. An important decision on such system is whether to move data to traditional processors (paying the communication costs), or performing computation where data is sitting, using a potentially slower processor. Hence, runtime environments that deal with that trade-off are extremely necessary. This work takes a first step towards a solution that considers Edge/Fog/In-situ in a dataflow runtime. We use Sucuri to manage the execution in a small system with a regular PC and a Parallella board. Experiments with text processing applications running with different input sizes, network latency and packet loss rates allow a discussion of scenarios where this approach would be fruitful.

关键词： Program processors Libraries computer architecture Runtime environment performance evaluation Field programmable gate arrays

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high-level dataflow programming for reconfigurable computing 26

High-level dataflow programming for reconfigurable computing

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26th IEEE international symposium on computer architecture and high performance computing workshops, SBAC-PADW 2014

作者： Sérot, J. Berry, F. Institut Pascal Université Blaise Pascal / CNRS Clermont-Ferrand France

ISBN: (纸本)9781479970148

In many application domains, FPGAS are now promoted as a way of getting round the restrictions of specific CPU designs on system scalability. However, in the current state-of-the art, programming FPGAS remains essentially a hardware-oriented activity, relying on dedicated hardware description languages such as VHDL or Verilog. Using these languages requires expertise in digital design and in practice this limits the applicability of FPGA-based solutions. This is particulary true for stream-processing applications, in which some processing must be carried out "on the fly" on digital data streams. In this context, the dataflow programming model offers a very effective way to reduce the gap between high-level formulations and low-level implementations. To support this claim, the authors have recently introduced CAPH, a domain specific language, offering a fully-automated compilation path from high-level dataflow descriptions to FPGA configuration for stream-processing applications. This paper is a introduction to the CAPH language, giving its motivations and main design principles and exposing the basic features of its syntax, semantics and compilation. It also points to experimental results showing that, at least for stream-processing applications, the dataflow model of computation, used jointly as a programming model and an execution model, can offer a very effective way to conciliate abstraction and efficiency when programming FPGAS. © 2014 IEEE.

关键词： computer hardware description languages

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Task-specific restricted delegation 07

Task-specific restricted delegation

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16th international symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located workshops

作者： Alderman, Ian D. Livny, Miron Computer Sciences University of Wisconsin Madison

No abstract available

ISBN: (纸本)1595936734

No abstract available

关键词： PKI security distributed batch computing

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I/O performance of multiscale finite element simulations on HPC environments 34

I/O performance of multiscale finite element simulations on ...

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34th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Boito, Francieli Gomes, Antonio Tadeu A. Peyrondet, Louis Teylo, Luan Univ Bordeaux LaBRI INRIA Bordeaux INPCNRSUMR 5800 F-33400 Talence France Lab Nacl Comp Cient LNCC Av Getulio Vargas 333 BR-25651075 Petropolis RJ Brazil

ISBN: (数字)9781665451574

ISBN: (纸本)9781665451574

In this paper, we present MSLIO, a code to mimic the I/O behavior of multiscale simulations. Such an I/O kernel is useful for HPC research, as it can be executed more easily and more efficiently than the full simulations when researchers are interested in the I/O load only. We validate MSLIO by comparing it to the I/O performance of an actual simulation, and we then use it to test some possible improvements to the output routine of the MHM (Multiscale Hybrid Mixed) library.

关键词： high-performance computing parallel I/O numeric library I/O kernel mini-app multiscale simulation

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high-speed restoration of atomic force microscopy images using tikhonov regularization in GPGPU 26

High-speed restoration of atomic force microscopy images usi...

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26th IEEE international symposium on computer architecture and high performance computing workshops, SBAC-PADW 2014

作者： Quelhas, Klaus N. Cidade, Geraldo A. G. Farias, Ricardo COPPE/System Engineering Federal University of Rio de Janeiro Rio de Janeiro RJ Brazil Biophysics Institute Carlos Chagas Filho Federal University of Rio de Janeiro Rio de Janeiro RJ Brazil

ISBN: (纸本)9781479970148

The Atomic Force Microscopy (AFM) is a scanning probe technique widely used to produce nanometric scaled images of virtually any kind of non-conductive or biological surface. Depending on the scanning dimensions an expected AFM image structure is subjected to be modified by great amounts of external noise (low Signal/Noise ratios) - electrical or mechanical - and/or blurring due to the geometry of the measuring probe. In order to minimize such effects, image restoration techniques can be employed. The one based on the minimization of the Tikhonov's regularization functional is described, taking into account the characteristics of the measuring probe and the S/N ratio. This work proposes optimizations on both serial and parallel restoration algorithms, using CUDA library on a General Purpose Graphics Processing Unit, GPGPU, in terms of time performance and quality of restoration in regime of high speed imaging, one frame/sec or more. The results obtained are so far very promising, reaching speedups up to 43x over previous implementations. © 2014 IEEE.

关键词： Atomic force microscopy

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Strategies to Improve the performance of a Geophysics Model for Different Manycore Systems 29

Strategies to Improve the Performance of a Geophysics Model ...

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8th international symposium on computer architecture and high performance computing (SBAC-PADW)

作者： Serpa, Matheus S. Cruz, Eduardo H. M. Diener, Matthias Krause, Arthur M. Navaux, Philippe O. A. Farres, Albert Rosas, Claudia Hanzich, Mauricio Panetta, Jairo Fed Univ Rio Grande do Sul UFRGS Informat Inst Porto Alegre RS Brazil BSC Barcelona Spain Aeronaut Inst Technol ITA Comp Sci Div Sao Jose Dos Campos SP Brazil

ISBN: (纸本)9781538648193

Many software mechanisms for geophysics exploration in Oil & Gas industries are based on wave propagation simulation. To perform such simulations, state-of-art HPC architectures are employed, generating results faster and with more accuracy at each generation. The software must evolve to support the new features of each design to keep performance scaling. Furthermore, it is important to understand the impact of each change applied to the software, in order to improve the performance as most as possible. In this paper, we propose several optimization strategies for a wave propagation model for five architectures: Intel Haswell, Intel Knights Corner, Intel Knights Landing, NVIDIA Kepler and NVIDIA Maxwell. We focus on improving the cache memory usage, vectorization, and locality in the memory hierarchy. We analyze the hardware impact of the optimizations, providing insights of how each strategy can improve the performance. The results show that NVIDIA Maxwell improves over Intel Haswell, Intel Knights Corner, Intel Knights Landing and NVIDIA Kepler performance by up to 17.9x.

关键词： Optimization computer architecture Program processors Mathematical model Acoustic waves Hardware Cache memory

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Best of SBAC-PAD 2012

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PARALLEL computing 2014年第9期40卷 512-513页

作者： Schnorr, Lucas Mello Alexandre Navaux, Philippe Olivier Univ Fed Rio Grande do Sul Inst Informat BR-91501970 Porto Alegre RS Brazil

This special issue presents new trends in computer architecture and in parallel and distributed systems. It is based on the best papers of the 24th international symposium on computer architecture and high performance computing, which was held in New York, NY, USA on October 24-26, 2012 in the Columbia University. The authors were invited to provide extended versions of the papers presented in the conference, taking into account suggestions by the double-blinded peer review process and comments gathered during the conference.

关键词： computer architecture Parallel and distributed systems high performance computing

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RACB: Resource aware cache bypass on GPUs 26

RACB: Resource aware cache bypass on GPUs

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26th IEEE international symposium on computer architecture and high performance computing workshops, SBAC-PADW 2014

作者： Dai, Hongwen Kartsaklis, Christos Li, Chao Janjusic, Tomislav Zhou, Huiyang Department of Electrical and Computer Engineering North Carolina State University Raleigh United States Computer Science and Mathematics Division Oak Ridge National Laboratory Oak Ridge United States

ISBN: (纸本)9781479970148

Caches are universally used in computing systems to hide long off-chip memory access latencies. Unlike CPUs, massive threads running simultaneously on GPUs bring a tremendous pressure on memory hierarchy. As a result, the limitation of cache resources becomes a bottleneck for a GPU to exploit thread-level parallelism (TLP) and memory-level parallelism (MLP) and achieve high performance. In this paper, we propose a mechanism to bypass L1D and L2 cache based on the availability of cache resources. Our proposed mechanism is based on the observation that a huge number of stalls coming from limited cache resources prohibit GPUs from providing a higher throughput. So we propose Resource Aware Cache Bypass (RACB) with minor hardware changes to eliminate such stalls to improve performance. We examine the effectiveness of this approach when applied to L1D and L2 cache separately as well as together. Evaluation results with NVIDIA computing SDK show that RACB generally improves performance the most when applied to both L1D and L2 cache, which is up to 88.05% and on an average of 16.73%;additionally, energy is saved up to 22.35% and on an average of 5.88% with minor hardware overheads. © 2014 IEEE.

关键词： Graphics processing unit

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