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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

共 5225 条记录，以下是171-180 订阅

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The case for flexible ISAs: unleashing hardware and software 29

The case for flexible ISAs: unleashing hardware and software

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29th international symposium on computer architecture and high performance computing SBAC-PAD

作者： Auler, Rafael Borin, Edson Univ Estadual Campinas UNICAMP Campinas SP Brazil

ISBN: (纸本)9781509012336

For a long time the Instruction Set architecture (ISA) has been the firm contract between software and hardware. This firm contract plays an important role by decoupling the development of software from hardware micro-architectural features, enabling both to evolve independently. Nonetheless, it also condemns the ISA to become larger, more cluttered and inefficient as new instructions are incorporated over the years and deprecated instructions are left untouched to keep legacy compatibility. In this work we propose OpenISA, a flexible ISA that enables both the software and the hardware to evolve independently and discuss how OpenISA 1.0 was designed to enable efficient OpenISA software emulation on alien ISAs, which is key to free the user from hardware lock-ins. Our results show that software compiled to OpenISA can be latter emulated on x86 and ARM processors with very little overhead achieving near native performance, under 10% for the majority of programs.

关键词： Emulation Program processors Payloads Hardware Recycling computer architecture

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On-chip Parallel Photonic Reservoir computing using Multiple Delay lines 32

On-chip Parallel Photonic Reservoir Computing using Multiple...

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32nd IEEE international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Hasnain, Syed Ali Mahapatra, Rabi Texas A&M Univ Dept Comp Sci & Engn College Stn TX 77843 USA

ISBN: (纸本)9781728199245

Silicon-Photonics architectures have enabled high speed hardware implementations of Reservoir computing (RC). With a delayed feedback reservoir (DFR) model, only one non-linear node can be used to perform RC. However, the delay is often provided by using off-chip fiber optics which is not only space inconvenient but it also becomes architectural bottleneck and hinders to scalability. In this paper, we propose a completely on-chip photonic RC architecture for high performance computing, employing multiple electronically tunable delay lines and micro-ring resonator (MRR) switch for multi-tasking. Proposed architecture provides 84% less error compared to the state-of-the-art standalone architecture in [8] for executing NARMA task. For multi-tasking, the proposed architecture shows 80% better performance than [8]. The architecture outperforms all other proposed architectures as well. The on-chip area and power overhead of proposed architecture due to delay lines and MRR switch are 0.0184mm(2) and 26mW respectively.

关键词： Reservoir computing (RC) Delayed Feedback Reservoir (DFR) Recurrent Neural Network (RNN) Mach Zehnder Interferometer (MZI) Micro ring Resonator (MRR)

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Evaluating polynomials in several variables and their derivatives on a GPU computing processor

Evaluating polynomials in several variables and their deriva...

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26th IEEE international Parallel and Distributed Processing symposium (IPDPS) / Workshop on high performance Data Intensive computing

作者： Verschelde, Jan Yoffe, Genady Univ Illinois Dept Math Stat & Comp Sci Chicago IL 60607 USA

ISBN: (纸本)9780769546766

In order to obtain more accurate solutions of polynomial systems with numerical continuation methods we use multiprecision arithmetic. Our goal is to offset the overhead of double double arithmetic accelerating the path trackers and in particular Newton's method with a general purpose graphics processing unit. In this paper we describe algorithms for the massively parallel evaluation and differentiation of sparse polynomials in several variables. We report on our implementation of the algorithmic differentiation of products of variables on the NVIDIA Tesla C2050 computing Processor using the NVIDIA CUDA compiler tools.

关键词： algorithmic differentiation compute unified device architecture (CUDA) graphics processing unit (GPU) massively parallel polynomial evaluation Speelpenning product

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Environmentally responsible middleware: An altruistic behavior model for distributed middleware components 07

Environmentally responsible middleware: An altruistic behavi...

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16th international symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located workshops

作者： Meehean, Joe Livny, Miron Department of Computer Sciences University of Wisconsin-Madison 1210 W. Dayton St. Madison WI 53706

No abstract available

ISBN: (纸本)1595936734

No abstract available

关键词： altruistic behavior model middleware resource exhaustion

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CSinParallel and synergy for rapid incremental addition of PDC into CS curricula

CSinParallel and synergy for rapid incremental addition of P...

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26th IEEE international Parallel and Distributed Processing symposium (IPDPS) / Workshop on high performance Data Intensive computing

作者： Brown, Richard Shoop, Elizabeth St Olaf Coll Dept Math Stat & Comp Sci Northfield MN 55057 USA Macalester Coll Dept Math Stat & Comp Sci St Paul MN 55105 USA

ISBN: (纸本)9780769546766

How can the CS education community shift to teach more parallel and distributed computing (PDC) soon enough to prepare its graduates for their careers? The CSinParallel project implements strategies that would accomplish such a shift. An Early Adopter project to correlate CSinParallel materials and NSF/TCPP Curricular Recommendations is described. Citing research on scalability of innovations, such synergistic collaborations offer hope for scalably and rapidly adding PDC to undergraduate CS education.

关键词： education parallel computing distributed computing curriculum curricular change computer science

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FFT optimizations and performance assessment targeted towards satellite and airborne radar processing 32

FFT optimizations and performance assessment targeted toward...

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32nd IEEE international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Schlemon, Maron Naghmouchi, Jamin German Aerosp Ctr DLR Microwaves & Radar Inst Oberpfaffenhofen Germany Innovat Gesell TU Braunschweig mbH Next Generat Comp Braunschweig Germany

ISBN: (纸本)9781728199245

Following the re-invention of the FFT algorithm by Cooley and Tukey in 1965, a lot of effort has been invested into optimization of this algorithm and all its variations. In this paper, we discuss its use and optimization for current and future radar applications, and give a brief survey on implementations that have claimed relatively high advantages in terms of performance over existing solutions. Correspondingly, we present an in-depth analysis of state-of-the-art solutions and our own implementation that will allow the reader to evaluate the performance improvements on a fair basis. Therefore, we discuss the development of a high-performance Fast Fourier Transform (FFT) using an enhanced Radix-4 decimation in frequency (DIF) algorithm, compare it against the Fastest Fourier Transform in the West (FFTW) autotuned library as well as other solutions and frameworks.

关键词： FFT Radix-4 DIF high performance Algorithms Parallel computing Embedded computing SAR Chirp Compression

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Exploratory analysis of raw data files through dataflows 26

Exploratory analysis of raw data files through dataflows

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26th IEEE international symposium on computer architecture and high performance computing workshops, SBAC-PADW 2014

作者： Silva, Vitor De Oliveira, Daniel Mattoso, Marta Computer Science - COPPE Federal University of Rio de Janeiro Rio de Janeiro Brazil Institute of Computing Fluminense Federal University Niteroi Brazil

ISBN: (纸本)9781479970148

Scientific applications generate raw data files in very large scale. Most of these files follow a standard format established by the domain area application, like HDF5, NetCDF and FITS. These formats are supported by a variety of programming languages, libraries and programs. Since they are in large scale, analyzing these files require writing a specific program. Generic data analysis systems like database management systems (DBMS) are not suited because of data loading and data transformation in large scale. Recently there have been several proposals for indexing and querying raw data files without the overhead of using a DBMS, such as noDB, RAW and FastBit. Their goal is to offer query support to the raw data file after a scientific program has generated it. However, these solutions are focused on the analysis of one single large file. When a large number of files are all related and required to the evaluation of one scientific hypothesis, the relationships must be managed manually or by writing specific programs. The proposed approach takes advantage of existing provenance data support from Scientific Workflow Management Systems (SWfMS). When scientific applications are managed by SWfMS, the data is registered along the provenance database at runtime. Therefore, this provenance data may act as a description of theses files. When the SWfMS is dataflow aware, it registers domain data all in the same database. This resulting database becomes an important access method to the large number of files that are generated by the scientific workflow execution. This becomes a complementary approach to the single raw data file analysis support. In this work, we present our dataflow approach for analyzing data from several raw data files and evaluate it with the Montage application from the astronomy domain. © 2014 IEEE.

关键词： Data handling

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Processing Neocognitron of Face Recognition on high performance Environment Based on GPU with CUDA architecture

Processing Neocognitron of Face Recognition on High Performa...

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20th international symposium on computer architecture and high performance computing

作者： Poli, Gustavo Saito, Jose Hiroki Mari, Joao F. Zorzan, Marcelo R. Univ Fed Sao Carlos Dept Comp BR-13560 Sao Carlos SP Brazil

ISBN: (纸本)9780769534237

This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an artificial neural network, proposed by Fukushima and collaborators, constituted of several hierarchical stages of neuron layers, organized in. two-dimensional matrices called cellular planes. For the high performance computation of Face Recognition application using Neocognitron it was used CUDA (Compute Unified Device architecture) as API (Application Programming Interface) between the CPU and the GPU, from GeForce 8800 GTX of NVIDIA company, with 128 ALU's. As face image databases it was used a face database created at UFS-Car and the CMU-PIE (Carnegie Mellon University Pose, Illumination and Expression) database. The load balancing was achieved through the use of cellular connections as threads organized in blocks, following the CUDA philosophy), of development. The results showed the feasibility of this type of device as a massively parallel data processing tool, and that smaller the granularity and the data dependency of the parallel processing, better is its performance.

关键词： Graphics processing unit

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Experiences in Teaching a Specialty Multicore computing Course

Experiences in Teaching a Specialty Multicore Computing Cour...

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26th IEEE international Parallel and Distributed Processing symposium (IPDPS)

作者： Strazdins, Peter E. Australian Natl Univ Res Sch Comp Sci Canberra ACT 0200 Australia

ISBN: (纸本)9780769546766

We detail the design and experiences in delivering a specialty multicore computing course whose materials are openly available. The course ambitiously covers three multicore programming paradigms: shared memory (OpenMP), device (CUDA) and message passing (RCCE), and involves significant practical work on their respective platforms: an UltraSPARC T2, Fermi GPU and the Intel Single-Chip Cloud computer. Specialized multicore architecture topics include chip multiprocessing, virtualization support, on-chip accelerators and networks, transactional memory and speculative execution. The mode of delivery emphasizes the relationship between programming performance and the underlying computer architecture, necessitating the need to provide suitable infrastructure in the form of instrumented test programs and the use of performance evaluation tools. Further infrastructure had to be created to facilitate the safe, convenient and efficient use by students on the GPU and Single-Chip Cloud computer. The programming assignments, based on the theme of the LINPACK benchmark, also required significant infrastructure for reliably determining correctness and assisting debugging. While the course assumed as background knowledge an introductory computer systems and concurrency course, we found that students could learn device programming in a short time, by building on their knowledge of shared memory programming. However, we found that more time is needed for learning message passing. We also found that, provided students had a suitably strong computer systems background, they could successfully meet the course's learning objectives, although the skill of correctly interpreting performance data remains difficult to learn when suitable performance analysis tools are not available.

关键词： multicore computing parallel computing computing education

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Stack-tagged dataflow 26

Stack-tagged dataflow

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26th IEEE international symposium on computer architecture and high performance computing workshops, SBAC-PADW 2014

作者： Santiago, Leandro Marzulo, Leandro A.J. Goldstein, Brunno F. Alves, Tiago A.O. França, Felipe M.G. Dep. de Informática e Ciência da Computação Instituto de Matemática e Estatística - IMe Universidade Do Estado Do Rio de Janeiro - UERJ Rio de Janeiro Brazil Programa de Engenharia de Sistemas e Computação COPPE Universidade Federal Do Rio de Janeiro Rio de Janeiro Brazil

ISBN: (纸本)9781479970148

Dynamic Dataflow allows simultaneous execution of instructions in different iterations of a loop, boosting parallelism exploitation. In this model, operands are tagged with their associated instance number, incremented as they go through the loop. Instruction execution is triggered when all input operand with the same tag become available. However, this traditional tagging mechanism often requires the generation of several control instructions to manipulate tags and guarantee the correct matching. To address this problem, this work presents Stack- Tagged Dataflow, a tagging mechanism that uses stacks of tags to reduce control overheads in dataflow, while isolating context from different nested loops. Push instructions at the beginning of loops will create a new context, while Pop instructions, at the end of the loop, will restore the original context tags. Experimental results show that Stack-Tagged Dataflow is a viable solution, suggesting that a hybrid compiling approach can be used to enable Stack- Tags only when needed. © 2014 IEEE.

关键词： data flow computing program control structures context isolation dataflow control overhead reduction nested loops pop instructions push instructions stack-tagged dataflow tagging mechanism Assembly computer architecture Context Libraries Parallel processing Tagging Virtual machining Dataflow Parallel Programming Stack Tag data flow TAGGING program control structures virtual machines Parallel programming computer architecture Furnace conveyors PARALLEL PROCESSING (computerS) Loops Libraries assemblies NESTED LOOPS virtual machining instruction

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