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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

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Evaluating the Influence of Graph Characteristics on Parallel Algorithms for Derived Graph Structures 31

Evaluating the Influence of Graph Characteristics on Paralle...

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31st IEEE international Conference on high performance computing, Data, and Analytics workshops, HiPCW 2024

作者： Pathak, Maulein Kapila, Samarth Sabharwal, Yogish Gupta, Neelima Dept of Computer Science University of Delhi India Keshav Mahavidyalaya University of Delhi India University Of British Columbia Vancouver Canada IBM Research India India Dept of Computer Science University of Delhi India

ISBN: (纸本)9798331509118

This work investigates how graph characteristics affect the quality of derived graphs, specifically focusing on graph spanners. Graph spanners retain all vertices and a subset of edges while preserving shortest distances with an allowable stretch, making them essential for efficiently approximating graph structures. We emphasize recent advancements in parallel algorithms for constructing spanners in sparse graphs, building on the work of Miller et al. and Forster et al. By extracting key graph properties and employing data analysis techniques-such as correlation analysis, linear regression, and random forest regression-we examine the relationships between these characteristics and the size of the derived graphs, which is vital for optimizing spanner construction in real-world applications. © 2024 IEEE

关键词： Graph algorithms

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A Software Platform to Support Disaggregated Quantum Accelerators

A Software Platform to Support Disaggregated Quantum Acceler...

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2024 workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC workshops 2024

作者： Kaya, Ercument Echavarria, Jorge Farooqi, Muhammad Nufail Swierkowska, Aleksandra Hopf, Patrick Mete, Burak Burgholzer, Lukas Wille, Robert Schulz, Laura Schulz, Martin Leibniz Supercomputing Centre Bavarian Academy of Sciences and Humanities Garching Germany Munich Germany Munich Germany

ISBN: (纸本)9798350355543

Quantum computers are making their way into high performance computing (HPC) centers as next-generation accelerators. Due to their physical implementation as mostly large appliances in separate racks, their number in typical data centers is significantly lower than the number of nodes offloading work to them, unlike the case with GPU accelerators. As a consequence, they form large-scale disaggregated infrastructures that pose a number of integration challenges due to their diverse implementation technologies and their need to be used as a shared resource for optimal utilization. Running hybrid high performance computing-Quantum computing (HPCQC) applications in HPC environments, where the quantum portion is offloaded to the quantum processing units (QPUs), requires sophisticated resource management strategies to optimize resource utilization and performance. In this paper, we present one aspect of the Munich Quantum Software Stack (MQSS) - a Just-In-Time (JIT) compilation and execution software stack for quantum and hybrid quantum-HPC workloads - beneficial for integrating disaggregated quantum accelerators into traditional HPC workflows. MQSS is centered around a series of novel contributions aimed at optimizing the compilation process while managing the disaggregated resources ensuring efficient utilization of all available quantum resources. The key stages of our JIT compilation stack involve hardware-agnostic optimizations, quantum circuit cutting - when necessary - and a novel hardware platform selection process. Included here is description of the use of the MQSS's Quantum Device Management Interface (QDMI), a unified interface between the software stack and the quantum accelerators, which allows connection to several, potentially different, quantum resources. Our methodology demonstrates notable advancements in HPCQC integration workflows, offering researchers a powerful framework for leveraging quantum computational capabilities. Overall, our work represents

关键词： Disaggregated Infrastructures HPCQC Integration Hybrid Software Stacks Quantum computing Quantum Systems

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TEACHING Platform for Human-Centric Autonomous Applications: Design and Overview 24

TEACHING Platform for Human-Centric Autonomous Applications:...

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33rd international symposium on high-performance Parallel and Distributed computing (HPDC)

作者： De Caro, Valerio Chronis, Christos Coppola, Massimo Lomonaco, Vincenzo Gallicchio, Claudio Tserpes, Konstantinos Bacciu, Davide Univ Pisa Dept Comp Sci Pisa Italy Harokopio Univ Athens Dept Informat & Telemat Athens Greece CNR Informat Sci & Technol Inst Pisa Italy

ISBN: (纸本)9798400704130

The TEACHING project enhances AI applications in pervasive environments via Humanistic Intelligence, fostering synergy between humans and Cyber-Physical Systems of Systems (CPSoS). Here, we present the TEACHING Platform, a microservice-based framework providing the technological advancements to represent humans and CPSoS as containerized software models that interact to mutually empower each other.

关键词： Human-centered computing Artificial Intelligence Software

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high-Quality I/O Bandwidth Prediction with Minimal Data via Transfer Learning Workflow 36

High-Quality I/O Bandwidth Prediction with Minimal Data via ...

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36th IEEE international symposium on computer architecture and high-performance computing, SBAC-PAD 2024

作者： Povaliaiev, Dmytro Liem, Radita Kunkel, Julian Lofstead, Jay Carns, Philip RWTH Aachen University Chair of High Performance Computing IT Center Aachen Germany Georg-August Universität Göttingen/GWDG Göttingen Germany Sandia National Laboratory Albuquerque United States Argonne National Laboratory Lemont United States

ISBN: (纸本)9798350356168

Providing a high-quality performance prediction has the potential to enhance various aspects of a cluster, such as devising scheduling and provisioning policies, guiding procurement decisions, suggesting candidate applications for tuning, and identifying probable scaling and porting challenges. Creating such a prediction for the I/O metrics is still challenging, however, due to the intricate interplay of multiple cluster components, making this an ideal case for machine learning. Nevertheless, achieving the required accuracy level with machine learning calls for a substantial amount of high-quality data, which is often a difficult challenge for most HPC clusters. In this work we explore the use of transfer learning to predict the applications' I/O bandwidth based on a public dataset. As a result, our experiment can provide an I/O bandwidth prediction for a different cluster comparable to the current state-of-the-art result while employing 100 times less data than needed to construct the base model. Furthermore, we evaluate potential future improvements of the proposed workflow. © 2024 IEEE.

关键词： Adversarial machine learning

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Leveraging In-band Network Telemetry for Automated DDoS Detection in Production Programmable Networks: The AmLight Use Case

Leveraging In-band Network Telemetry for Automated DDoS Dete...

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2024 workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC workshops 2024

作者： Sahin, Hadi Bezerra, Jeronimo Brito, Italo Frez, Renata Chergarova, Vasilka Lopez, Luis Fernandez Ibarra, Julio Rede Nacional de Ensino e Pesquisa Rio de Janeiro Brazil Florida International University Center for Internet Augmented Research and Assessment MiamiFL33199 United States University of São Paulo Faculty of Medicine São Paulo Brazil

ISBN: (纸本)9798350355543

Programmable data planes have provided great flexibility in defining the behaviors of packet forwarding switches, routers, and network interface cards (NICs). The In-band Network Telemetry (INT) technology further increased network operators' potential to manage packet flows by enabling real-time and customizable monitoring of packets without creating much overhead on the network. These recent advancements in networking technology have generated significant research interest and activity, including studies on INT-based DDoS detection and mitigation mechanisms. However, in practice, INT technology has not been fully realized yet, especially in detecting network anomalies in real-time. There is also a gap in the literature that provides a comparative evaluation of INT-based solutions against existing alternatives. In this paper, we aim to implement a holistic real-time INT-based DDoS detection mechanism. The proposed mechanism will retrieve INT data from the network, analyze it using machine learning (ML) models in real-time, and send the information to the control plane. We will also compare the performance of using INT to detect DDoS attacks against sFlow-based detection. © 2024 IEEE.

关键词： DDoS detection INT Machine Learning P4 programmable plane

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Architecting Space Microdatacenters: A System-level Approach 31

Architecting Space Microdatacenters: A System-level Approach

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Bleier, Nathan Eason, Rick Lembeck, Michael Kumar, Rakesh University of Michigan Department of Electrical Engineering & Computer Science Ann ArborMI United States University of Illinois Department of Electrical and Computer Engineering UrbanaIL United States University of Illinois Department of Aerospace Engineering UrbanaIL United States

ISBN: (纸本)9798331506476

Server-based computing in space has been recently proposed due to potential benefits in terms of capability, latency, security, sustainability, and cost. Despite this, there has been no work asking the question: how should we architect systems for server-based computing in space when considering overall cost. This paper presents a Total Cost of Ownership (TCO)-based approach to architecture of server-based computing systems for space (Space Microdatacenters - SμDC) for processing data produced by low Earth orbit (LEO)-based Earth observation (EO) satellites. We show that power of compute is the primary factor in determining SμDC TCO, though the dependence is sublinear. Second, the impact of compute mass, monetary cost, and communication on TCO is relatively insignificant. Third, architectures with the highest \frac{\text { FLOPs }}{W} provide much higher performance per TCO {\} even if they have poor \frac{FLOPs}{\}. We leverage these insights to advocate extreme heterogeneity designs for SμDCs. These designs reduce SμDC TCO by 116× in spite of poor \frac{{FLOPs}}{\} characteristics. We also show that (a) collaborative compute constellations - constellations in which EO satellites are also equipped with compute hardware - further improve SμDC TCO by 1.31 to 1.74×, (b) a distributed architecture reduces TCO by 10% over a monolithic architecture, and (c) low monetary cost of compute can be leveraged to provide near zero cost compute overprovisioning which improves an SμDC's availability significantly and supports graceful degradation. Overall, this is the first paper on cost-aware architecture and optimization of a SμDC. © 2025 IEEE.

关键词： Digital storage

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MegIS: high-performance, Energy-Efficient, and Low-Cost Metagenomic Analysis with In-Storage Processing 51

MegIS: High-Performance, Energy-Efficient, and Low-Cost Meta...

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ACM/IEEE 51st Annual international symposium on computer architecture (ISCA)

作者： Ghiasi, Nika Mansouri Sadrosadati, Mohammad Mustafa, Harun Gollwitzer, Arvid Firtina, Can Eudine, Julien Mao, Haiyu Lindegger, Joel Cavlak, Meryem Banu Alser, Mohammed Park, Jisung Mutlu, Onur Swiss Fed Inst Technol Zurich Switzerland POSTECH Pohang South Korea

ISBN: (纸本)9798350326598;9798350326581

Metagenomics, the study of the genome sequences of diverse organisms in a common environment, has led to significant advances in many fields. Since the species present in a metagenomic sample are not known in advance, metagenomic analysis commonly involves the key tasks of determining the species present in a sample and their relative abundances. These tasks require searching large metagenomic databases containing information on different species' genomes. Metagenomic analysis suffers from significant data movement overhead due to moving large amounts of low-reuse data from the storage system to the rest of the system. In-storage processing can be a fundamental solution for reducing this overhead. However, designing an in-storage processing system for metagenomics is challenging because existing approaches to metagenomic analysis cannot be directly implemented in storage effectively due to the hardware limitations of modern SSDs. We propose MegIS, the first in-storage processing system designed to significantly reduce the data movement overhead of the end-to-end metagenomic analysis pipeline. MegIS is enabled by our lightweight design that effectively leverages and orchestrates processing inside and outside the storage system. Through our detailed analysis of the end-to-end metagenomic analysis pipeline and careful hardware/software co-design, we address in-storage processing challenges for metagenomics via specialized and efficient 1) task partitioning, 2) data/computation flow coordination, 3) storage technology-aware algorithmic optimizations, 4) data mapping, and 5) lightweight in-storage accelerators. MegIS's design is flexible, capable of supporting different types of metagenomic input datasets, and can be integrated into various metagenomic analysis pipelines. Our evaluation shows that MegIS outperforms the state-of-the-art performance-and accuracy-optimized software metagenomic tools by 2.7x-37.2x and 6.9x-100.2x, respectively, while matching the accuracy of

关键词： Metagenomic Analysis Near-Data Processing Storage

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CereSZ: Enabling and Scaling Error-bounded Lossy Compression on Cerebras CS-2 24

CereSZ: Enabling and Scaling Error-bounded Lossy Compression...

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33rd international symposium on high-performance Parallel and Distributed computing (HPDC)

作者： Song, Shihui Huang, Yafan Jiang, Peng Yu, Xiaodong Zheng, Weijian Di, Sheng Cao, Qinglei Feng, Yunhe Xie, Zhen Cappello, Franck Univ Iowa Iowa City IA USA Stevens Inst Technol Hoboken NJ USA Argonne Natl Lab Lemont IL USA St Louis Univ St Louis MO USA Univ North Texas Denton TX USA Binghamton Univ Binghamton NY USA

ISBN: (纸本)9798400704130

Today's scientific applications running on supercomputers produce large volumes of data, leading to critical data storage and communication challenges. To tackle the challenges, error-bounded lossy compression is commonly adopted since it can reduce data size drastically within a user-defined error threshold. Previous work has shown that compression techniques can significantly reduce the storage and I/O overhead while retaining good data quality. However, the existing compressors are mainly designed for CPU and GPU. As new AI chips are being incorporated into supercomputers and increasingly used for accelerating scientific computing, there is a growing demand for efficient data compression on the new architecture. In this paper, we propose an efficient lossy compressor, CereSZ, based on the Cerebras CS-2 system. The compression algorithm is mapped onto Cerebras using both data parallelism and pipeline parallelism. In order to achieve a balanced workload on each processing unit, we propose an algorithm to evenly distribute the pipeline stages. Our experiments with six scientific datasets demonstrate that CereSZ can achieve a throughput from 227.93 GB/s to 773.8 GB/s, 2.43x to 10.98x faster than existing GPU compressors.

关键词： Error-bounded Lossy Compression AI-Optimized architecture Parallel computing Scientific Simulation high-speed Compressor

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Multi-Dimensional Vector ISA Extension for Mobile In-Cache computing 31

Multi-Dimensional Vector ISA Extension for Mobile In-Cache C...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Khadem, Alireza Fujiki, Daichi Chen, Hilbert Gu, Yufeng Talati, Nishil Mahlke, Scott Das, Reetuparna University of Michigan United States Institute of Science Tokyo Japan

ISBN: (纸本)9798331506476

In-cache computing technology transforms existing caches into long-vector compute units and offers low-cost alternatives to building expensive vector engines for mobile CPUs. Unfortunately, existing long-vector Instruction Set architecture (ISA) extensions, such as RISC-V Vector Extension (RVV) and Arm Scalable Vector Extension (SVE), provide only onedimensional strided and random memory accesses. While this is sufficient for typical vector engines, it fails to effectively utilize the large Single Instruction, Multiple Data (SIMD) widths of incache vector engines. This is because mobile data-parallel kernels expose limited parallelism across a single dimension. Based on our analysis of mobile vector kernels, we introduce a long-vector Multi-dimensional Vector ISA Extension (MVE) for mobile in-cache computing. MVE achieves high SIMD resource utilization and enables flexible programming by abstracting cache geometry and data layout. The proposed ISA features multi-dimensional strided and random memory accesses and efficient dimension-level masked execution to encode parallelism across multiple dimensions. Using a wide range of data-parallel mobile workloads, we demonstrate that MVE offers significant performance and energy reduction benefits of 2.9 × and 8.8 ×, on average, compared to the SIMD units of a commercial mobile processor, at an area overhead of 3.6%. © 2025 IEEE.

关键词： Vectors

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Ensemble Simulations on Leadership computing Systems

Ensemble Simulations on Leadership Computing Systems

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2024 workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC workshops 2024

作者： Georgiadou, Antigoni Monge-Camacho, Henry Sohail, Tanvir Ghosh, Swarnava Parambathu, Arjun Valiya Asthagiri, Dilipkumar N. Bykov, Dmytro Athawale, Tushar Beck, Thomas L. National Center for Computational Sciences Oak RidgeTN United States Oak Ridge National Laboratory Oak RidgeTN United States University of Delaware DE United States

ISBN: (纸本)9798350355543

Scientific productivity can be enhanced through workflow management tools, relieving large high performance computing (HPC) system users from the tedious tasks of scheduling and designing the complex computational execution of scientific applications. This paper presents a study on the usage of ensemble workflow tools to accelerate science using the Summit and Frontier supercomputing systems. The research aims to connect science domain simulations using Oak Ridge Leadership computing Facility (OLCF) supercomputing platforms with ensemble workflow methods in order to accelerate HPC-enabled discovery and boost scientific impact. We present the coupling, porting and optimization of Radical-Cybertools on three applications: Chroma, NAMD and LAMMPS. The tools augment traditional HPC monolithic runs with a pilot scheduler. Lessons-learned are discussed for physics, biology and materials science applications. We discuss intrinsic limitations of coupling and porting ensemble workflow tools to applications that run on large HPC systems. The origins of technical challenges and their solutions developed during the implementation process are discussed. Data management strategies, OLCF's policies for ensembles, and natively supported workflow tools are also summarized.1 © 2024 IEEE.

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