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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

共 5225 条记录，以下是241-250 订阅

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Automated GPU Grid Geometry Selection for OpenMP Kernels 30

Automated GPU Grid Geometry Selection for OpenMP Kernels

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Lloyd, Taylor Chikin, Artem Kedia, Sanket Jain, Dhruv Amaral, Jose Nelson Univ Alberta Edmonton AB Canada IIT Kharagpur Kharagpur W Bengal India

ISBN: (纸本)9781538677698

Modern supercomputers are increasingly using GPUs to improve performance per watt. Generating GPU code for target regions in OpenMP 4.0, or later versions, requires the selection of grid geometry to execute the GPU kernel. Existing industrial-strength compilers use a simple heuristic with arbitrary numbers that are constant for all kernels. After characterizing the relationship between region features, grid geometry and performance, we built a machine-learning model that successfully predicts a suitable geometry for such kernels and results in a performance improvement with a geometric mean of 5% across the benchmarks studied. However, this prediction is impractical because the overhead of the predictor is too high. A careful study of the results of the predictor allowed for the development of a practical low-overhead heuristic that resulted in a performance improvement of up to 7 times with a geometric mean of 25.9%. This paper describes the methodology to build the machine-learning model, and the practical low-overhead heuristic that can be used in industry-strong compilers.

关键词： GPUs heterogeneous computing OpenMP Machine Learning Grid Geometry

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Hiding Communication Delays in Clustered Microarchitectures

Hiding Communication Delays in Clustered Microarchitectures

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20th international symposium on computer architecture and high performance computing

作者： LaDuca, Robert J. Sharkey, Joseph J. Ponomarev, Dmitry V. BAE Systems Assured Information Security State University of New York at Binghamton

ISBN: (纸本)9780769534237

Clustered microarchitectures represent a viable solution for addressing wire delays in communication-bound architectures by partitioning monolithic datapath structures into smaller components. While supporting high frequencies, clustered processors usually degrade the instruction throughput due to the inter-cluster communication delays and non-balanced workload distribution. In this paper, we propose and evaluate novel instruction steering policies to reduce or eliminate cross-cluster communication delays while respecting workload balance. Our first technique hides the inter-cluster communication latencies by examining operand readiness information. The proposed policy steers instructions with two register sources to the cluster predicted to generate the last-produced operand. While the later-produced operand is being generated, the transport of the early-produced operand can occur in parallel, hiding the communication delay. Our second technique steers an entire group of instructions co-renamed in a cycle to the same cluster if the number of intra-group register dependencies exceed a threshold. This is done in a round-robin fashion in order to reduce impact on workload balancing.

关键词： computer architecture

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Courses in high-performance computing for scientists and engineers

Courses in high-performance computing for scientists and eng...

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26th IEEE international Parallel and Distributed Processing symposium (IPDPS)

作者： Vuduc, Richard Czechowski, Kenneth Chandramowlishwaran, Aparna Choi, Jee Whan Georgia Inst Technol Sch Computat Sci & Engn Atlanta GA 30332 USA

ISBN: (纸本)9780769546766

This paper reports our experiences in reimplementing an entry-level graduate course in high-performance parallel computing aimed at physical scientists and engineers. These experiences have directly informed a significant redesign of a junior/senior undergraduate course, Introduction to high-performance computing (CS 4225 at Georgia Tech), which we are implementing for the current Spring 2012 semester. Based on feedback from the graduate version, the redesign of the undergraduate course emphasizes peer instruction and hands-on activities during the traditional lecture periods, as well as significant time for end-to-end projects. This paper summarizes our anecdotal findings from the graduate version's exit surveys and briefly outlines our plans for the undergraduate course.

关键词： parallel computing computational science and engineering education peer instruction

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Object Placement for high Bandwidth Memory Augmented with high Capacity Memory 29

Object Placement for High Bandwidth Memory Augmented with Hi...

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29th international symposium on computer architecture and high performance computing SBAC-PAD

作者： Laghari, Mohammad Unat, Didem Koc Univ Comp Sci & Engn Istanbul Turkey

ISBN: (纸本)9781509012336

high bandwidth memory (HBM) is a new emerging technology that aims to improve the performance of bandwidth-limited applications. Even though it provides high bandwidth, it must be augmented with DRAM to meet the memory capacity requirement of many applications. Due to this limitation, objects in an application should be optimally placed on the heterogeneous memory subsystems. In this study, we propose an object placement algorithm that places program objects to fast or slow memories in case the capacity of fast memory is insufficient to hold all the objects to increase the overall application performance. Our algorithm uses the reference counts and type of references (read or write) to make an initial placement of data. In addition, we perform various memory bandwidth benchmarks to be used in our placement algorithm on Intel Knights Landing (KNL) architecture. Not surprisingly high bandwidth memory sustains higher read bandwidth than write bandwidth, however, placing write-intensive data on HBM results in better overall performance because write-intensive data is punished by the DRAM speed more severely compared to read-intensive data. Moreover, our benchmarks demonstrate that if a basic block makes references to both types of memories, it performs worse than if it makes references to only one type of memory in some cases. We test our proposed placement algorithm with 6 applications under various system configurations. By allocating objects according to our placement scheme, we are able to achieve a speedup of up to 2x.

关键词： high bandwidth memory object placement MCDRAM DRAM KNL

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Task Scheduling in Sucuri Dataflow Library 28

Task Scheduling in Sucuri Dataflow Library

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28th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Silva, Rafael J. N. Goldstein, Brunno Santiago, Leandro Sena, Alexandre C. Marzulo, Leandro A. J. Alves, Tiago A. O. Franca, Felipe M. G. Univ Estado Rio De Janeiro Inst Matemat & Estat Rio De Janeiro Brazil Univ Fed Rio de Janeiro COPPE Programa Engn Sistemas & Comp Rio de Janeiro Brazil

ISBN: (纸本)9781509048441

Sucuri is a minimalistic Python library that provides dataflow programming through a reasonably simple syntax. It allows transparent execution on computer clusters and natural exploitation of parallelism. In Sucuri, programmers instantiate a dataflow graph, where each node is assigned to a function and edges represent data dependencies between nodes. The original implementation of Sucuri adopts a centralized scheduler, which incurs high communication overheads, specially in clusters with a large number of machines. In this paper we modify Sucuri so that each machine in a cluster will have its own scheduler. Before execution, the dataflow graph is partitioned, so that nodes can be distributed among the machines of the cluster. In runtime, idle workers will grab tasks from a ready queue in their local scheduler. Experimental results confirm that the solution can reduce communication overheads, improving performance in larger clusters.

关键词： Dataflow computing high performance computing Task Scheduling

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Improving virtual machine consolidation for heterogeneous cloud computing datacenters 31

Improving virtual machine consolidation for heterogeneous cl...

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31st international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Magri Rodrigues, Joao Antonio de Oliveira, Fabiola Martins C. Lobato, Renata Spolon Spolon, Roberta Manacero, Aleardo Borin, Edson Sao Paulo State Univ UNESP Dept Comp Sci & Stat Sao Paulo SP Brazil Univ Estadual Campinas Inst Comp Campinas SP Brazil Sao Paulo State Univ UNESP Fac Sci Bauru SP Brazil

ISBN: (纸本)9781728141947

Datacenters in cloud computing systems may consist of thousands of computing nodes and communication devices, requiring virtual machine placement to optimize resources utilization. Heterogeneous environments of current datacenters have not been properly evaluated yet when the number of processing nodes and network devices is considered. This paper presents an approach to place virtual machines to minimize both the number of employed computing nodes and communication costs in heterogeneous environments. We evaluate our results against other known algorithms to show the efficiency of the proposed approach, which outperforms a state-of-the-art algorithm with a result of up to 13% better for network improvement while achieves the same number of computing nodes.

关键词： cloud computing virtual machine placement heterogeneous systems

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EDGELESS: A Software architecture for Stateful FaaS at the Edge 24

EDGELESS: A Software Architecture for Stateful FaaS at the E...

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33rd international symposium on high-performance Parallel and Distributed computing (HPDC)

作者： Cicconetti, Claudio Carlini, Emanuele Hetzel, Raphael Mortier, Richard Paradell, Antonio Sauer, Markus CNR Pisa Italy Tech Univ Munich TUM Sch CIT Munich Germany Univ Cambridge Cambridge England Worldline Barcelona Spain Siemens AG Munich Germany

EDGELESS is a serverless platform targeting edge computing that supports widely distributed deployments using heterogeneous devices. We present its components, architecture, and programming model. Our working prototyp... 详细信息

ISBN: (纸本)9798400704130

关键词： serverless computing edge computing cloud-continuum resource-constrained devices

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Quantum Virtual Machine: A scalable model to optimize energy savings and resource management 27

Quantum Virtual Machine: A scalable model to optimize energy...

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IEEE 27th international symposium on computer architecture and high performance computing

作者： Monteiro, Andre Felipe Loques, Orlando Univ Fed Fluminense Inst Comp Programa Pos Grad Comp Niteroi RJ Brazil Ctr Fed Educ Tecnol Celso Suckow Fonseca CEFET RJ Petropolis Brazil

ISBN: (纸本)9781467380119

This work presents a model for managing Virtual Application Servers (VAS) on cluster-based web servers. In addition to providing energy savings, our model has linear scalability and defines a default processing virtual web server, known as Quantum Virtual Machine (QVM). A set of QVM performs a Logical Web Server (LWS), which operates in a flexible manner, changing its performance and power consumption depending on the workload of the applications. Concepts of agile VAS clone, co-allocation of VAS in the same core, and Dynamic Voltage and Frequency Scaling (DVFS) are used in the model, enabling rapid configuration actions and a fine-grained QoS control. The experiments evaluate the effectiveness of the proposed model by means of power consumption reduction and QoS violation as compared to the Linux CPU governors and state-of-the-art approaches based on optimization. The results show our model conserves up to 51.8% of the energy required by a cluster designed for peak workload scenario, with a negligible impact on the applications performance.

关键词： Power-aware computing Resource management Scalability Virtualization Web server clusters

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Energy-efficient online resource provisioning for cloud-edge platforms via multi-armed bandits 34

Energy-efficient online resource provisioning for cloud-edge...

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34th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Rey-Jouanchicot, Jordan del Castillo, Juan Angel Lorenzo Zuckerman, Stephane Veronica Belmega, E. CY Cergy Paris Univ CY Tech Cergy France CY Cergy Paris Univ ETIS UMR 8051 ENSEA CNRS F-95000 Cergy France Univ Gustave Eiffel CNRS LIGM F-77454 Marne La Vallee France

ISBN: (数字)9781665451574

ISBN: (纸本)9781665451574

Edge computing is a new paradigm in which data are locally collected, aggregated and preprocessed before being sent to a Cloud platform. Edge devices, typically IoT objects, are characterized by limited computational capabilities, alongside high energy efficiency operations. In smart building or smart city applications, the overall amount of available IoT devices may account for an important computational capacity. Aggregating the idle CPU cycles of several devices would allow performing on-site parallel and distributed computing, while reusing the available resources in the network. Timely and important computational tasks such as video surveillance processing, HPC jobs, or deep neural network training, can be performed with local available resources. This includes local servers or a private, on-site cloud, as opposed to the use of public clouds, thus avoiding security issues and fostering energy efficiency. An ongoing research topic in such a distributed and volatile context is to design novel algorithms for resource provisioning that allow tasks to be distributed over a set of available IoT devices in an efficient manner. This work presents two online, adaptive and robust scheduling techniques, based on the UCB and EXP3 Multi-Armed Bandit algorithms (MABs), for resource management in Cloud-Edge computing based environments while improving performance and reducing energy consumption. The novelty of our adapted algorithms lies in the fact that we explicitly account for unavailable computing IoT devices resulting in a time-varying available set of arms at each stage. Our numerical results show the high relevance of our approach in reaching optimal provisioning policies in time-varying environments.

关键词： Cloud Edge computing resource provisioning online learning multi-armed bandits

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Convolution Operators for Deep Learning Inference on the Fujitsu A64FX Processor 34

Convolution Operators for Deep Learning Inference on the Fuj...

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34th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Dolz, Manuel F. Martinez, Hector Alonso, Pedro Quintana-Orti, Enrique S. Univ Jaume I Castellon Castellon de La Plana Spain Univ Cordoba Cordoba Spain Univ Politecn Valencia Valencia Spain

ISBN: (数字)9781665451550

ISBN: (纸本)9781665451550

The convolution operator is a crucial kernel for many computer vision and signal processing applications that rely on deep learning (DL) technologies. As such, the efficient implementation of this operator has received considerable attention in the past few years for a fair range of processor architectures. In this paper, we follow the technology trend toward integrating long SIMD (single instruction, multiple data) arithmetic units into high performance multicore processors to analyse the benefits of this type of hardware acceleration for latency-constrained DL workloads. For this purpose, we implement and optimise for the Fujitsu processor A64FX, three distinct methods for the calculation of the convolution, namely, the lowering approach, a blocked variant of the direct convolution algorithm, and the Winograd minimal filtering algorithm. Our experimental results include an extensive evaluation of the parallel scalability of these three methods and a comparison of their global performance using three popular DL models and a representative dataset.

关键词： Convolutional neural networks high performance SIMD arithmetic units ARM-based A64FX processor

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