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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

共 5225 条记录，以下是251-260 订阅

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Flexible high-performance access to distributed storage resources 9

Flexible high-performance access to distributed storage reso...

引用

9th IEEE international symposium on high performance Distributed computing

作者： Patten, CJ Hawick, KA Univ Adelaide Dept Comp Sci Distributed & High Performance Comp Grp Adelaide SA 5005 Australia

ISBN: (纸本)0769507840

We describe a software architecture for storage services in computational grid environments. Based upon a lightweight message-passing paradigm, the architecture enables the provision and composition of active, distributed storage services. These services can then cooperatively provide access to distributed storage in a manner potentially optimized for dataset and resource environments. We report on the design and implementation of a distributed file system and a dataset-specific satellite imagery service using the architecture. We discuss data movement and storage issues and implications for future work with the architecture.

关键词： computer architecture Distributed computing File servers File systems Grid computing Memory Network servers Peer to peer computing Prefetching Satellites

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A metascheduler for the Grid 11

A metascheduler for the Grid

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11th IEEE international symposium on high performance Distributed computing (HPDC-11)

作者： Vadhiyar, SS Dongarra, JJ Univ Tennessee Comp Sci Dept Knoxville TN 37996 USA

ISBN: (纸本)0769516866

With the advent of Grid computing, scheduling strategies for distributed heterogeneous systems have either become irrelevant or have to be extended significantly to support Grid dynamics. In this paper, we describe a metascheduling architecture for a Grid system that takes into account both the application and system level considerations. Results are presented to demonstrate the usefulness of the metascheduler.

关键词： computer architecture computer science Contracts Distributed computing Dynamic scheduling Grid computing Libraries Lifting equipment Mars Processor scheduling

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The Right Metric for Efficient Supercomputing: A Ten-Year Retrospective 30

The Right Metric for Efficient Supercomputing: A Ten-Year Re...

引用

30th IEEE international Parallel and Distributed Processing symposium (IPDPS)

作者： Hsu, Chung-Hsing Feng, Wu-chun Oak Ridge Natl Lab Comp Sci & Math Div Oak Ridge TN 37831 USA Virginia Tech Dept Comp Sci Blacksburg VA 24061 USA

ISBN: (纸本)9781509036820

About ten years ago, we presented the results of an effort to identify the "right metric" for efficient supercomputing at this workshop, The Workshop on high-performance, Power-Aware computing. In this paper, we review the advances that the community has made in this area of research. The intention of this ten-year retrospective is two-fold: (1) to acknowledge the past work through a historical narrative and (2) to highlight the essence of the remaining issues in this research.

关键词： retrospective metrics energy efficiency high performance computing

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Teaching by example: using analogies and live coding demonstrations to teach parallel computing concepts to undergraduate students

Teaching by example: using analogies and live coding demonst...

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26th IEEE international Parallel and Distributed Processing symposium (IPDPS) / Workshop on high performance Data Intensive computing

作者： Giacaman, Nasser Univ Auckland Dept Elect & Comp Engn Auckland 1 New Zealand

ISBN: (纸本)9780769546766

This paper details recent experience in teaching parallel computing concepts to undergraduate computer Science students. By taking a practical approach in delivering the material, students are shown to have grasped essential multi-threading concepts in Java, ensuring they are able to implement the necessary skills themselves. The motivation for parallel computing is clearly demonstrated early in the course, to immediately convince students of the importance in developing their parallel computing skills, should they wish to be effective software developers. Within only 4 weeks, students are able to correctly and efficiently multi-thread a sequential desktop application (with a Graphical User Interface) that is both responsive (does not freeze the user interface) and performant (utilises the underlying multi-core processor). The student evaluations confirm that using live coding demonstrations and analogies were most helpful in learning parallel computing.

关键词： PARALLEL PROCESSING (computerS) Students Analogy User Interface Device Component desktop application college student Ants Pedagogy Teaching

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An Optimized Reconfigurable System for computing the Phylogenetic Likelihood on DNA Data

An Optimized Reconfigurable System for Computing the Phyloge...

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26th IEEE international Parallel and Distributed Processing symposium (IPDPS) / Workshop on high performance Data Intensive computing

作者： Berger, Simon A. Alachiotis, Nikolaos Stamatakis, Alexandros Heidelberg Inst Theoret Studies Exelixis Lab Sci Comp Grp Heidelberg Germany

ISBN: (纸本)9780769546766

The Phylogenetic Likelihood Function (PLF) is an important statistical function for evaluating phylogenetic trees. To this end, the PLF is the computational kernel of all state-of-the-art likelihood-based phylogenetic inference programs. Typically, it accounts for more than 85% of total execution time in such programs. We present a substantially improved hardware architecture for computing the PLF based on previous experiences with implementing the PLF on reconfigurable logic. Our new design is optimized for computing the PLF on four-state (DNA) input data. It is also adapted to the computational requirements of real-world tree inference programs and completely independent of the specific tree search algorithm at hand. Furthermore, we describe how our architecture can be modified and adapted to handle general n-state data, such as protein (20 states) or RNA secondary structure data (6, 7, or 16 states, depending on the model). Finally, we designed an interface mechanism such that our PLF hardware architecture can interact with the widely-used phylogenetic inference tool RAxML. We deploy FPGA technology to verify the correctness of the architecture and to evaluate performance.

关键词： Likelihood Functions hardware architecture execution time Reconfigurable logic architecture Building construction updated design configurability accuracy class

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Peer-to-peer checkpointing arrangement for mobile grid computing systems 07

Peer-to-peer checkpointing arrangement for mobile grid compu...

引用

16th international symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located workshops

作者： Darby III, Paul J. Tzeng, Nian Feng Center for Advanced Computer Studies University of Louisiana at Lafayette Lafayette LA 70504

ISBN: (纸本)1595936734

This paper deals with a novel, distributed, QoS-aware, peer-to-peer checkpointing arrangement component for Mobile Grid (MoG) computing systems middleware. Checkpointing is more crucial in MoG systems than in their wired counterparts due to node mobility and less reliable wireless links resulting in frequent and dynamic connections and disconnections. Having determined the globally optimal checkpoint arrangement to be NP-complete, we consider ReD, our Reliability Driven (ReD) protocol, employing QoS-aware heurisitcs, for constucting superior peer-to-peer checkpointing arrangements efficiently.

关键词： Distributed computer systems

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high-performance Ensembles of Online Sequential Extreme Learning Machine for Regression and Time Series Forecasting 30

High-Performance Ensembles of Online Sequential Extreme Lear...

引用

30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Grim, Luis Fernando L. Gradvohl, Andre Leon S. Univ Campinas FT UNICAMP Sch Technol Limeira SP Brazil Fed Inst Educ Sci & Technol Sao Paulo IFSP Piracicaba SP Brazil

ISBN: (纸本)9781538677698

Ensembles of Online Sequential Extreme Learning Machine algorithm are suitable for forecasting Data Streams with Concept Drifts. Nevertheless, data streams forecasting require high-performance implementations due to the high incoming samples rate. In this work, we proposed to tune-up three ensembles, which operates with the Online Sequential Extreme Learning Machine, using high-performance techniques. We reimplemented them in the C programming language with Intel MKL and MPI libraries. The Intel MKL provides functions that explore the multithread features in multicore CPUs, which expands the parallelism to multiprocessors architectures. The MPI allows us to parallelize tasks with distributed memory on several processes, which can be allocated within a single computational node, or spread over several nodes. In summary, our proposal consists of a two-level parallelization, where we allocated each ensemble model into an MPI process, and we parallelized the internal functions of each model in a set of threads through Intel MKL. Thus, the objective of this work is to verify if our proposals provide a significant improvement in execution time when compared to the respective conventional serial approaches. For the experiments, we used a synthetic and a real dataset. Experimental results showed that, in general, the high-performance ensembles improve the execution time, when compared with its serial version, performing up to 10-fold faster.

关键词： high-performance computing Machine Learning Time Series Forecasting Regression Data Streams Concept Drift

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Proceedings - symposium on computer architecture and high performance computing

Proceedings - Symposium on Computer Architecture and High Pe...

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IEEE 27th international symposium on computer architecture and high performance computing workshops, SBAC-PADW 2015

ISBN: (纸本)9781467386210

The proceedings contain 20 papers. The topics discussed include: using hardware transactional memory to enable speculative trace optimization;energy consumption and scalability evaluation for software transactional memory on a real computing environment;replicating the performance evaluation of an n-body application on a manycore accelerator;characterizing anomalies of a multicore ARMv7 cluster with parallel N-body simulations;MDACCER: modified distributed assessment of the closeness CEntrality ranking in complex networks for massively parallel environments;intra-clustering: accelerating on-chip communication for data parallel architectures;Kanga: a skeleton-based generic interface for parallel programming;painless parallelism on heterogeneous hardware leveraging the functional paradigm;CHAOS-MCAPI: an optimized mechanism to support multicore parallel programming;and exploiting parallelism in linear algebra kernels through dataflow execution.

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Approximate Memory with Protected Static Allocation 34

Approximate Memory with Protected Static Allocation

引用

34th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Fabricio Filho, Joao Felzmann, Isaias Wanner, Lucas Univ Estadual Campinas Inst Comp Campinas Brazil Univ Tecnol Fed Parana Campus Campo Mourao Curitiba Parana Brazil

ISBN: (数字)9781665451550

ISBN: (纸本)9781665451550

Approximate memories provide energy savings or performance improvements at the cost of occasional errors in stored data. Applications that tolerate errors on their data profit from this trade-off by controlling these errors to not affect critical data. This control usually involves programmer intervention with annotations in the source code. To avoid annotations, some techniques protect critical data that are common on many applications, isolating specific memory regions from errors. In this work, we propose and explore alternatives for the protection of application critical data by managing a supervisor execution environment with an approximate memory system. We expose only dynamically allocated data to errors with secure data manipulation through an approximate allocation scheme that divide stored data based on the approximation of the heap area. We evaluate 6 applications with different data access profiles and obtain up to 20% of energy savings.

关键词： Approximate computing Approximate Memory Error Tolerance

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Modifying HMMER3 to Run Efficiently on the Cori Supercomputer using OpenMP Tasking 32

Modifying HMMER3 to Run Efficiently on the Cori Supercompute...

引用

32nd IEEE international Parallel and Distributed Processing symposium (IPDPS)

作者： Arndt, William Lawrence Berkeley Natl Lab Natl Energy Res Sci Comp Ctr Berkeley CA 94720 USA

ISBN: (纸本)9781538655559

HMMER3 is biological sequence search suite used in significant volume on systems hosted at the National Energy Research Scientific computing Center. This heavy usage has revealed ways that HMMER3 underutilizes the resources available in an HPC environment such as the Manycore architecture Knights Landing processors available in the Cori supercomputer. After rigorous performance analysis it was determined that the thread architecture of HMMER3 is the most promising optimization target to increase throughput and efficiency. A refactoring effort introduced an OpenMP task based threading design, the ability to respond to imbalanced computation with work stealing, and input buffering to eliminate a large amount of redundant parsing. These efforts have been implemented and in production on Cori for over a year. In that time they have simplified the best practice for use of HMMER3 in workflows and conserved hundreds of thousands of CPU hours.

关键词： Multithreading Multicore Processing OpenMP high performance computing Bioinformatics

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